ZL50012
Flexible 512-ch Digital Switch
Data Sheet
Features
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512 channel x 512 channel non-blocking switch at
2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
Rate conversion between the ST-BUS inputs and
ST-BUS outputs
Per-stream ST-BUS input with data rate selection
of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
Per-stream ST-BUS output with data rate
selection of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s; the output data rate can be different
than the input data rate
Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
Per-stream input channel and input bit delay
programming with fractional bit delay
Per-stream output channel and output bit delay
programming with fractional bit advancement
Multiple frame pulse outputs and reference clock
outputs
Per-channel constant throughput delay
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April 2006
Ordering Information
ZL50012/QCC 160 Pin LQFP
Trays
ZL50012/GDC 144 Ball LBGA Trays
ZL50012QCG1 160 Ball LQFP* Trays, Bake & Drypack
ZL50012GDG2 144 Ball LBGA** Trays, Bake & Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Per-channel high impedance output control
Per-channel message mode
Per-channel pseudo random bit sequence
(PRBS) pattern generation and bit error detection
Control interface compatible to Motorola non-
multiplexed CPUs
Connection memory block programming
capability
IEEE-1149.1 (JTAG) test port
3.3V I/O with 5 V tolerant input
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V
DD
V
SS
RESET
ODE
STi0-15
S/P Converter
Data Memory
P/S Converter
STo0-15
FPi
CKi
Output HiZ Control
Input Timing
Connection Memory
STOHZ0-15
Microprocessor
Interface
and
Internal
Output Timing
FPo0
CKo0
FPo1
CKo1
FPo2
CKo2
IC0 - 4
CLKBYPS
ICONN0 - 2
Registers
APLL
Test Port
V
DD_APLL
V
SS_APLL
D15 - 0
A11 - 0
DTA
TMS
TDO
TCK
Figure 1 - ZL50012 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved.
TRST
SG1
TM1
TM2
R/W
DS
CS
TDI
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
