ZL50021
Changes Summary
The following table captures the changes from January 2006 to November 2006.
Page
1
Item
Change
Updated Ordering Information.
Data Sheet
The following table captures the changes from the October 2004 issue.
Page
39, 77, 79
Item
Section 12.1, “DPLL Timing Modes“ on
page 39
RCCR Register bits “FDM1 - 0” on page 77
RCSR Register bits “DPM1 - 0” on page 79
•
Change
The on-chip DPLL’s normal, holdover, automatic,
and freerun modes are now collectively referred
to as DPLL timing modes instead of operation
modes. This change is to avoid confusion with
the two main device operating modes; the
master and slave modes.
Section 12.1.3.1 and Section 12.1.3.2 added to
clarify the DPLL’s automatic reference switching
with and without preference operations in
Automatic Timing Mode.
Added description to specify that the device
should not be in freerun and fast lock modes
simultaneously. This is important in order to
avoid incorrect output frame pulse generation.
Clarified threshold calculations.
Added a table footnote to specify that the
DPLL’s fastlock and freerun modes should not
be set simultaneously.
Added description to clarify that only two
consecutive references can be used in
automatic timing mode with a preferred
reference.
Added description to specify that the DPLL’s
fastlock and freerun modes should not be set
simultaneously.
40, 41
Section 12.1.3.1, “Automatic Reference
Switching Without Preferences“ on page 40
and Section 12.1.3.2, “Automatic
Reference Switching With Preference“ on
page 41
Section 12.1.4, “Freerun Mode“ on page
43, and Section 15.4, “Fast Locking Mode“
on page 46
Table 36, Lock Detector Threshold
Register (LDTR) Bits
Table 39, “Bandwidth Control Register
(BWCR) Bits” Note 3.
Table 40, “Reference Change Control
Register (RCCR) Bits” Bits “PRS1 - 0“ and
Bits “PMS2 - 0“
Table 40, “Reference Change Control
Register (RCCR) Bits”, Bits “FDM1 - 0“
•
43, 46
•
73
75
•
•
76
•
77
•
10
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