ZL50021
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Data Sheet
Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and
output data rates can differ
Per-stream high impedance control outputs (STOHZ) for up to 16 output streams
Per-stream input bit delay with flexible sampling point selection
Per-stream output bit and fractional bit advancement
Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation
Multiple frame pulse and reference clock outputs
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
Input frame pulses: 61 ns, 122 ns, 244 ns
Per-channel constant or variable throughput delay for frame integrity and low latency applications
Per Stream Bit Error Rate Test circuits
Per-channel high impedance output control
Per-channel message mode
Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
Connection memory block programming
Supports ST-BUS and GCI-Bus standards for input and output timing
IEEE-1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Applications
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PBX and IP-PBX
Small and medium digital switching platforms
Wireless base stations and controllers
Remote access servers and concentrators
Multi service access platforms
Digital Loop Carriers
Computer Telephony Integration
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
