ZL50021
Enhanced 4 K Digital Switch with
Stratum 3 DPLL
Data Sheet
Features
•
4096-channel x 4096-channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and/or
16.384 Mbps
32 serial TDM input, 32 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 3
specifications
Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
•
•
Ordering Information
ZL50021GAC
256 Ball PBGA
ZL50021QCC
256 Lead LQFP
ZL50021QCG1
256 Lead LQFP*
ZL50021GAG2
256 Ball PBGA**
November 2006
•
•
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Trays
Trays
Trays, Bake &
Drypack
Trays, Bake &
Drypack
•
•
•
Programmable key DPLL parameters (filter corner
frequency, locking range, auto-holdover
hysteresis range, phase slope, lock detector
range)
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Output streams can be configured as bi-
directional for connection to backplanes
V
DD_CORE
V
DD_IO
V
DD_COREA
V
DD_IOA
V
SS
RESET
ODE
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
REF0
REF1
REF2
REF3
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ
Control
STOHZ[15:0]
DPLL
Output Timing
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
OSC_EN
OSC
Internal Registers &
Microprocessor Interface
Test Port
OSCo
DS_RD
R/W_WR
Figure 1 - ZL50021 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
D[15:0]
A[13:0]
OSCi
TRST
TDi
TMS
TCK
IRQ
TDo
CS