ZL50022
Changes Summary
The following table captures the changes from January 2006 to November 2006.
Page
1
Item
Change
Updated Ordering Information.
Data Sheet
The following table captures the changes from the October 2004 issue.
Page
39, 70, 71
Item
Section12.1, “DPLL Timing Modes“ on
page 39
RCCR Register bits “FDM1 - 0” on page 70
RCSR Register bits “DPM1 - 0” on page 71
•
Change
The on-chip DPLL’s normal, holdover, automatic,
and freerun modes are now collectively referred
to as DPLL timing modes instead of operation
modes. This change is to avoid confusion with
the two main device operating modes; the
master and slave modes.
Section 12.1.3.1 and Section 12.1.3.2 added to
clarify the DPLL’s automatic reference switching
with and without preference operations in
Automatic Timing Mode.
Clarified threshold calculations.
Added description to clarify that only two
consecutive references can be used in
automatic timing mode with a preferred
reference.
40
Section12.1.3.1, “Automatic Reference
Switching Without Preferences“ on page 40
and Section12.1.3.2, “Automatic Reference
Switching With Preferences“ on page 41
Table 33, Lock Detector Threshold
Register (LDTR) Bits
Table 36, “Reference Change Control
Register (RCCR) Bits” Bits “PRS1 - 0“ and
Bits “PMS2 - 0“
•
67
69
•
•
10
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