ZL50023
Enhanced 4 K Digital Switch
Data Sheet
Features
•
4096 channel x 4096 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps and 16.384 Mbps
32 serial TDM input, 32 serial TDM output
streams
Output streams can be configured as bi-
directional for connection to backplanes
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
Per-stream high impedance control outputs
(STOHZ) for 16 output streams
Per-stream input bit delay with flexible sampling
point selection
•
•
•
•
•
•
•
Ordering Information
ZL50023GAC
256 Ball PBGA Trays
ZL50023QCC
256 Lead LQFP Trays
ZL50023GAG2 256 Ball PBGA** Trays, Bake & Drypack
**Pb Free Tin/Silver/Copper
-40°C to +85°C
January 2006
•
•
•
•
Per-stream output bit and fractional bit
advancement
Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
Four frame pulse and four reference clock outputs
Three programmable delayed frame pulse outputs
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
Input frame pulses: 61 ns, 122 ns, 244 ns
Per-channel constant or variable throughput delay
for frame integrity and low latency applications
•
•
V
DD_CORE
V
DD_IO
V
DD_COREA
V
DD_IOA
V
SS
RESET
ODE
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ
Control
STOHZ[15:0]
Output Timing
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
TDi
D[15:0]
DS_RD
A[13:0]
R/W_WR
Figure 1 - ZL50023 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
TRST
TMS
TCK
TDo
CS
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
