ZL50075
32 K Channel Digital Switch with High Jitter
Tolerance, Rate Conversion per Group of
2 Streams (8, 16, 32 or 64 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Features
•
32,768 channel x 32,768 channel non-blocking
digital Time Division Multiplex (TDM) switch at
65.536 Mbps or 32.768 Mbps or using a
combination of rates
16,384 channel x 16,384 channel non-blocking
digital TDM switch at 16.384 Mbps
8,192 channel x 8,192 channel non-blocking
digital TDM switch at 8.192 Mbps
High jitter tolerance with multiple input clock
sources and frequencies
Up to 64 serial TDM input streams, divided into
32 groups with 2 input streams per group
Up to 64 serial TDM output streams, divided into
32 groups with 2 output streams per group
Per-group input and output data rate conversion
selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output
data group rates can differ
Per-group input bit delay for flexible sampling
point selection
Per-group output fractional bit advancement
Two sets of output timing signals for interfacing
additional devices
VDD_CORE
VDD_IO
VSS
January 2006
Ordering Information
ZL50075GAC
324 Ball PBGA
Trays
ZL50075GAG2 324 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
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-40°C to +85°C
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Per-channel A-Law/µ-Law Translation
Per-channel constant or variable throughput delay
for frame integrity and low latency applications
Per-stream Bit Error Rate (BER) test circuits
Per-channel high impedance output control
Per-channel force high output control
Per-channel message mode
Control interface compatible with Intel and
Motorola 16 bit non-multiplexed buses
Connection memory block programming
Supports ST-BUS and GCI-Bus standards for
input and output timing
IEEE 1149.1 (JTAG) test port
3.3 V I/O with 5V tolerant inputs; 1.8 V core
voltage
ODE
PWR
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•
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Input
Group 0
STiA0
STiB0
Output
Group 0
Data Memory
S/P
Converter
Connection Memory
P/S
Converter
SToA0
SToB0
Input
Group 31
:
:
STiA31
STiB31
:
:
SToA31
SToB31
Output
Timing
Output
Group 31
Input
Timing
FPi0
CKi0
CK_SEL1-0
FPo1-0
CKo1-0
Timing
Microprocessor Interface
and Control Registers
Test Access
Port
IM
DS
CS
R/W
SIZ1-0
A18-0
DTA
WAIT
BERR
D15-0
TMS
TDi
TDo
TCK
Figure 1 - ZL50075 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
TRST
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