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ZL50114GAG 参数 Datasheet PDF下载

ZL50114GAG图片预览
型号: ZL50114GAG
PDF下载: 下载PDF文件 查看货源
内容描述: 128 ,256, 512和1024通道的CESoP处理器 [128, 256, 512 and 1024 Channel CESoP Processors]
分类和应用: 电信集成电路
文件页数/大小: 112 页 / 1041 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50110/11/12/14
128, 256, 512 and 1024 Channel CESoP
Processors
Data Sheet
Features
General
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
Grooming capability for Nx64 Kbps trunking
Ordering Information
ZL50110GAG
552 PBGA
Trays, Bake
ZL50111GAG
552 PBGA
Trays, Bake
ZL50112GAG
552 PBGA
Trays, Bake
ZL50114GAG
552 PBGA
Trays, Bake
ZL50110GAG2 552 PBGA** Trays, Bake
ZL50111GAG2 552 PBGA** Trays, Bake
ZL50112GAG2 552 PBGA** Trays, Bake
ZL50114GAG2 552 PBGA** Trays, Bake
**Pb Fee Tin Silver/Copper
&
&
&
&
&
&
&
&
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
April 2008
Circuit Emulation Services
Supports ITU-T Recommendation Y.1413 and
Y.1453
Supports IETF RFC4553 and RFC5086
Supports MEF8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP, with integral
per stream clock recovery
-40°C to +85°C
Direct connection to LIUs, framers, backplanes
Dual reference Stratum 4 and 4E DPLL for
synchronous operation
Network Interfaces
Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
TDM Interfaces
Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
H.110, H-MVIP, ST-BUS backplanes
Up to 1024 bi-directional 64 Kbps channels
System Interfaces
Flexible 32 bit host CPU interface (Motorola
PowerQUICC
compatible)
On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
H.110, H-MVIP, ST-BUS backplanes
Triple 100 Mbps MII Fast Ethernet
32 T1/E1, 8 J2, 2 T3/E3 ports
(L IU , F ra m e r, B a c kp la n e )
T rip le
P acket
In te rfa c e
MAC
(M II, G M II, T B I)
P e r P o rt D C O fo r
C lo c k R e c o v e ry
PW , RTP, UDP,
IP v4 , IP v6 , M P L S ,
E C ID , V L A N , U s e r
D e fin e d , O th e rs
O n C h ip P a c k e t M e m o ry
Backplane
(J itte r B u ffe r C o m p e n s a tio n fo r 1 6 -1 2 8 m s o f P a c k e t D e la y V a ria tio n )
Clocks
D u a l R e fe re n ce
S tra tu m 3 D P L L
H o st P ro ce ss o r
In te rfa ce
E x te rn a l M e m o ry
In te rfa c e (o p tio n a l)
3 2 -b it M o to ro la c o m p a tib le
D M A fo r s ig n a lin g p a c k e ts
Z B T -S R A M
(0 - 8 M b y te s )
Figure 1 - ZL50111 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.
TBI Gigabit Ethernet
TDM
In te rfa c e
M u lti-P ro to c o l
P acket
P ro c e s s in g
E n g in e
Dual Redudnat 1000 Mbps GMII/
or