ZL50115/16/17/18/19/20
32, 64 and 128 Channel CESoP
Processors
Data Sheet
Features
General
•
•
•
•
•
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
On chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 Kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
Ordering Information
ZL50115GAG
324 Ball PBGA
trays, bake
ZL50116GAG
324 Ball PBGA
trays, bake
ZL50117GAG
324 Ball PBGA
trays, bake
ZL50118GAG
324 Ball PBGA
trays, bake
ZL50119GAG
324 Ball PBGA
trays, bake
ZL50120GAG
324 Ball PBGA
trays, bake
ZL50115GAG2 324 Ball PBGA** trays, bake
ZL50116GAG2 324 Ball PBGA** trays, bake
ZL50117GAG2 324 Ball PBGA** trays, bake
ZL50118GAG2 324 Ball PBGA** trays, bake
ZL50119GAG2 324 Ball PBGA** trays, bake
ZL50120GAG2 324 Ball PBGA** trays, bake
**Pb Free Tin/Silver/Copper
&
&
&
&
&
&
&
&
&
&
&
&
dry
dry
dry
dry
dry
dry
dry
dry
dry
dry
dry
dry
pack
pack
pack
pack
pack
pack
pack
pack
pack
pack
pack
pack
February 2006
Circuit Emulation Services
•
•
•
•
•
Complies with ITU-T recommendation Y.1413
Complies with IETF PWE3 draft standards
CESoPSN and SAToP
Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP with integral
per-stream clock recovery
•
•
-40°C to +85°C
Up to 128 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
Customer Side Packet Interfaces
• 100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
(may also be used as a second provider side packet
interface)
Provider Side Packet Interfaces
•
100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
Customer Side TDM Interfaces
•
•
Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplane
4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplanes
TDM
Interface
(LIU, Framer, Backplane)
Multi-Protocol
Packet
Processing
Engine
PW, RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
Defined, Others
Dual
Packet
Interface
MAC
(MII, GMII, TBI)
Per Port DCO for
Clock Recovery
100 Mbps MII
Fast Ethernet
On Chip Packet Memory
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Dual Reference
Stratum 3 DPLL
Host Processor
Interface
32-bit Motorola compatible
DMA for signaling packets
Backplane
Clocks
JTAG
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
100 Mbps MII Fast Ethernet
or
1000 Mbps GMII/TBI Gigabit Ethernet
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
