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ZL50118GAG 参数 Datasheet PDF下载

ZL50118GAG图片预览
型号: ZL50118GAG
PDF下载: 下载PDF文件 查看货源
内容描述: 32,64和128个信道的CESoP处理器 [32, 64 and 128 Channel CESoP Processors]
分类和应用: 电信集成电路电信电路
文件页数/大小: 95 页 / 1211 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50115/16/17/18/19/20
1.0
Changes Summary
Data Sheet
The following table captures the changes from the July 2005 issue.
Page
38, 39
Item
Section 4.5 and Section 4.6.2
Change
Added external pull-up/pull-down resistor
recommendations for SYSTEM_RST,
SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
The following table captures the changes from the April 2005 issue.
Page
49
Section 6.3
Item
Change
Added Section 6.3 SYSTEM_CLK Considerations.
The following table captures the changes from the January 2005 issue.
Page
Item
Change
Clarified data sheet to indicate ZL5011x supports clock
recovery in both synchronous and asynchronous modes
of operation.
84
Figure 42
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to
conform with default MPC8260. Polarity of CPU_DREQ
and CPU_SDACK remains programmable through API.
84
Figure 43
The following table captures the changes from the November 2004 issue.
Page
38
Section 4.6.1
Item
Change
Added 5 kohm pulldown recommendation to GPIO
signals.
3
Zarlink Semiconductor Inc.