ZL50404
7.6
Buffer Management
Data Sheet
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the ZL50404. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool, as shown in Figure 8 on page 38.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the ZL50404, its destination port and class are as yet unknown, and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Three priority sections, one for each pair of the first six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the
region of the FDB corresponding to its class. As we have indicated, the eight classes use only two transmission
scheduling queues for RMAC ports (four queues for the MMAC & CPU ports), but as far as buffer usage is
concerned, there are still eight distinguishable classes.
Another segment of the FDB reserves space for each of the 6 ports — 5 ports for Ethernet and one CPU port (port
number 8). Each port has it’s own programmable source port reservation. These 6 reserved regions make sure that
no well-behaved source port can be blocked by another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the three priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in
the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port.
The following registers define the size of each section of the Frame data Buffer:
-
-
-
-
-
-
-
PR100_N - Port Reservation for RMAC Ports
PR100_CPU - Port Reservation for CPU Port
PRM - Port Reservation for MMAC Port
SFCB - Share FCB Size
C1RS - Class 1 Reserve Size (priority 2 & 3)
C2RS - Class 2 Reserve Size (priority 4 & 5)
C3RS - Class 3 Reserve Size (priority 6 & 7)
Temporary reservation
Per Class
Reservation
Per Source Port
Reservation
R
pri1
R
pri2
R
pri3
Shared Pool S
R
p0
R
p1
R
p2
R
p3
R
p8
(CPU)
R
p9
Figure 8 - Buffer Partition Scheme
See Buffer Allocation application note, ZLAN-47, for more information.
38
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
