ZL50404
Data Sheet
If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 10M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed
accordingly.
If the MMAC port is configured in Reverse MII mode, RXCLK is generated from REF_CLK and is equal to
REF_CLK/2 for 100M mode (no support for 10M Reverse MII mode). REF_CLK needs to be a 50 MHz clock in this
mode.
12.0
12.1
Hardware Statistics Counters
Hardware Statistics Counters List
ZL50404 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the
CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay
exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager). The
following is the wrapped signal sent to the CPU through the command block.
63
Other Status Bits
30
29
Status Wrapped Signal
Bytes Sent (D)
Unicast Frame Sent
Frame Send Fail
Flow Control Frames Sent
Non-Unicast Frames Sent
Bytes Received (Good and Bad) (D)
Frames Received (Good and Bad) (D)
Total Bytes Received (D)
Total Frames Received
Flow Control Frames Received
Multicast Frames Received
Broadcast Frames Received
Frames with Length of 64 Bytes
Jabber Frames
Frames with Length Between 65-127 Bytes
Oversize Frames
0
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
B[8]
B9]
B[10]
B[11]
B[12]
B[13]
B[14]
B[15]
0-d
1-L
1-U
2-I
2-u
3-d
4-d
5-d
6-L
6-U
7-l
7-u
8-L
8-U
9-L
9-U
44
Zarlink Semiconductor Inc.
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