ZL50404 参数 Datasheet PDF下载

ZL50404

Bit [2]:

Bit [6:3]:

Bit [7]:

Data Sheet

Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read

Reserved

Device Timeout Detected interrupt

13.3.4.8

INTP_MASK0 – Interrupt Mask for MAC Port 0,1

CPU Address:h310

Accessed by CPU (R/W)

The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)

-

-

1: Mask the interrupt

0: Unmask the interrupt

Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic

counter wraps around. Refer to hardware statistic counter for interrupt sources

Port 0 link change mask

Port 0 module detect mask

Reserved

Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic

counter wraps around. Refer to hardware statistic counter for interrupt sources.

Port 1 link change mask

Port 1 module detect mask

Reserved

Bit [0]:

Bit [1]:

Bit [2]:

Bit [3]:

Bit [4]:

Bit [5]:

Bit [6]:

Bit [7]

13.3.4.9

INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers

INTP_MASK1

CPU Address:h311 (Ports 2,3)

INTP_MASK4

CPU Address:h314 (Port CPU,MMAC)

13.3.4.10

RQS – Receive Queue Select

CPU Address:h323

Accessed by CPU (RW)

Select which receive queue is used.

Bit [0]:

Bit [1]:

Bit [2]:

Bit [3]:

Bit [4]:

Bit [5]:

Select Queue 0

Select Queue 1

Select Queue 2

Select Queue 3

Select Multicast Queue 0

Select Multicast Queue 1

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Zarlink Semiconductor Inc.