ZL50410
Managed 8-Port 10/100M +
1-Port 10/100/1000M Ethernet Switch
Data Sheet
Features
•
Integrated Single-Chip 10/100/1000 Ethernet
Switch
• Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
Operates stand-alone or can be cascaded with a
second ZL50410 to reach 16 ports
Embedded 2 Mbits (256 KBytes) internal memory
• supports up to 4 K byte frames
L2 switching
• MAC address self learning, up to 4 K MAC
addresses using internal table
• Supports IP Multicast with IGMP snooping, up
to 4 K IP Multicast groups
• Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
• Supports Ethernet multicasting and
broadcasting and flooding control
8/16-bit
or
Serial
December 2004
Ordering Information
ZL50410GDC208 Pin LBGA
-40°C to +85°C
•
VLAN Support
• Supports port-based VLAN and tagged-based
VLAN (IEEE 802.1Q), up to 4 K VLANs
• Supports both shared VLAN learning (SVL)
and independent VLAN learning (IVL)
• Supports Private VLAN Edge (Protected Ports)
CPU access supports the following interface
options:
• 8/16-bit parallel and Serial+MII interface in
managed mode
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I
2
C EEPROM
interface
Failover Features
• Rapid link failure detection using
hardware-generated heartbeat packets
•
•
•
•
•
C
P
U
ZL50410
MII
GMII / MII
8-Port 10/100M + 1G
Ethernet Switch
EEPROM
I
2
C
10/100/
1000
PHY
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
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