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ZL50418 参数 Datasheet PDF下载

ZL50418图片预览
型号: ZL50418
PDF下载: 下载PDF文件 查看货源
内容描述: 网管16端口10/100 M + 2端口1个G以太网交换机 [Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 163 页 / 2005 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50418
Managed 16-Port 10/100 M + 2-Port 1 G
Ethernet Switch
Data Sheet
Features
Integrated Single-Chip 10/100/1000 Mbps
Ethernet Switch
16 10/100 Mbps Autosensing, Fast Ethernet
Ports with RMII or Serial Interface (7WS). Each
port can independently use one of the two
interfaces
2 Gigabit Ports with GMII, PCS and 10/100
interface options per port
Gigabit port supports hot swap in managed
configuration.
Supports 8/16-bit CPU interface in managed
mode
Serial interface in unmanaged mode
Supports two Frame Buffer Memory domains
with SRAM at 100 MHz
Supports memory size 2 MB, or 4 MB
• Two SRAM domains (2 MB or 4 MB) are
required
Applies centralized shared memory architecture
Up to 64 K MAC addresses
Maximum throughput is 3.6 Gbps non-blocking
High performance packet forwarding (10.712 M
packets per second) at full wire speed
Ordering Information
ZL50418/GKC 553-pin HSBGA
-40°C to +85°C
February 2004
Provides port based and ID tagged VLAN support
(IEEE 802.1Q), up to 255 VLANs
Supports IP Multicast with IGMP snooping
Supports spanning tree with CPU, on per port or
per VLAN basis
Packet Filtering and Port Security
• Static address filtering for source and/or
destination MAC
• Static MAC address not subject to aging
Secure mode freezes MAC address learning.
Each port may independently use this mode.
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
Supports Ethernet multicasting and broadcasting
and flooding control
Supports per-system option to enable flow control
for best effort frames even on QoS-enabled ports
VLAN 1 MCT
Frame Data Buffer A
SRAM (1 M / 2 M)
VLAN 1 MCT
Frame Data Buffer B
SRAM (1 M / 2 M)
FDB Interface
LED
FCB
Frame Engine
Search
Engine
MCT
Link
16 x 10 /100
RMII
Ports 0 - 15
GMII/
PCS
Port
0
GMII/
PCS
Port
1
Management
Module
16-bit
Parallel/
Serial
CPU
Figure 1 - ZL50418 System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.