PCA0163A-LF
PHASE LOCKED LOOP
14118 Stowe Drive, Suite B | Poway, CA 92064
TEL: (858) 621-2700 | FAX: (858) 486-1927
Rev A1
PHASE NOISE (1 Hz BW, typical)
FEATURES
• Frequency Range:163.84 -
163.84 MHz
KHz
• Step Size:
80
•
- Style Package
CPLL
APPLICATIONS
• Telecommunications
• Satellite
Telemetry
•
VALUE
163.84 - 163.84
UNITS
MHz
PERFORMANCE SPECIFICATIONS
Frequency Range
-102
dBc/Hz
dBc
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
-10
-70
0±3
50
dBc
Power Output
dBm
Load Impedance
Step Size
80
kHz
1250
Charge Pump Output Current
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
3
5
mSec
mSec
°C
-40 to 85
Operating Temperature Range
Package Style
CPLL
POWER SUPPLY REQUIREMENTS
Supply Voltage (Vcc, nom.)
3
Vdc
mA
Supply Current (Icc, typ.)
21
All specifications are typical unless otherwise noted and subject to change without notice.
APPLICATION NOTES
• AN-107 : How to Solder Z-COMM VCOs / PLLs
• AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<
<100 MHz
Frequency Synthesizer: Analog Devices - ADF4001
© Z-Communications, Inc.
Page 1
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ZCOMM [ Z-COMMUNICATIONS, INC ]
