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ZVNL120G 参数 Datasheet PDF下载

ZVNL120G图片预览
型号: ZVNL120G
PDF下载: 下载PDF文件 查看货源
内容描述: n沟道增强模式低阈值垂直DMOS FET [N-CHANNEL ENHANCEMENT MODE LOW THRESHOLD VERTICAL DMOS FET]
分类和应用: 晶体晶体管功率场效应晶体管光电二极管
文件页数/大小: 3 页 / 51 K
品牌: ZETEX [ ZETEX SEMICONDUCTORS ]
 浏览型号ZVNL120G的Datasheet PDF文件第2页浏览型号ZVNL120G的Datasheet PDF文件第3页  
SOT223 N-CHANNEL ENHANCEMENT MODE
LOW THRESHOLD VERTICAL DMOS FET
ISSUE 2 - JANUARY 1996
FEATURES
* V
DS
- 200V
* R
DS(ON)
- 10Ω
7
ZVNL120G
D
PARTMARKING DETAIL - ZVNL120
D
G
S
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T
amb
=25°C
Pulsed Drain Current
Gate-Source Voltage
Power Dissipation at T
amb
=25°C
Operating and Storage Temperature Range
SYMBOL
V
DS
I
D
I
DM
V
GS
P
tot
T
j
:T
stg
VALUE
200
320
2
±
20
2
-55 to +150
UNIT
V
mA
A
V
W
°C
ELECTRICAL CHARACTERISTICS (at T
amb
= 25°C unless otherwise stated).
PARAMETER
Drain-Source Breakdown
Voltage
SYMBOL MIN.
BV
DSS
200
0.5
1.5
100
10
100
500
10
10
200
85
20
7
8
8
20
12
MAX. UNIT CONDITIONS.
V
V
nA
µA
µA
mA
mS
pF
pF
pF
ns
ns
ns
ns
V
DD
≈25V,
I
D
=250mA
V
DS
=25V, V
GS
=0V, f=1MHz
I
D
=1mA, V
GS
=0V
I
D
=1mA, V
DS
= V
GS
V
GS
=± 20V, V
DS
=0V
V
DS
=200V, V
GS
=0V
V
DS
=160V, V
GS
=0V,
T=125°C
(2)
V
DS
=25V, V
GS
=5V
V
GS
=5V, I
D
=250mA
V
GS
=3V, I
D
=125mA
V
DS
=25V, I
D
=250mA
Gate-Source Threshold Voltage V
GS(th)
Gate-Body Leakage
Zero Gate Voltage Drain
Current
On-State Drain Current(1)
Static Drain-Source On-State
Resistance (1)
I
GSS
I
DSS
I
D(on)
R
DS(on)
Forward Transconductance(1)(2) g
fs
Input Capacitance (2)
Common Source Output
Capacitance (2)
C
iss
C
oss
Reverse Transfer Capacitance (2) C
rss
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
t
d(on)
t
r
t
d(off)
t
f
(1) Measured under pulsed conditions. Width=300µs. Duty cycle
≤2%
(2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
3 - 420