eZ80F915005MOD
eZ80F91 Mini Enet Module Product Specification
6
Table 1. eZ80Acclaim! Development Platform
Peripheral Bus Connector J1 Identification
1,2
(Continued)
Pin #
27
28
29
33
34
35
36
39
40
41
42
43
44
45
46
49
50
51
52
Symbol
A23
CS0
CS3
F91_WE
CS0
D3
RTC_V
DD
D7
HALT_SLP
A13
WR
A12
A11
A14
A9
A16
A5
A15
A4
Signal Direction Active Level eZ80F91 Signal
Bidirectional
Output
Output
Input
Output
Bidirectional
Input
Bidirectional
Output
Bidirectional
Ouput
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
n/a
Low
Low
Low
Low
n/a
n/a
n/a
Low
n/a
Low
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Jumper on board
Note
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F91 Mini Enet Module schematics
on
pages 31 through 32.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23
should be below 10 pF to satisfy the timing requirements for the eZ80® CPU. All unused inputs
should be pulled to either V
DD
or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be
deactivated via software in the eZ80F91’s Peripheral Power-Down Register.
PS023602-0804
PRELIMINARY
Pin Description
ZILOG [ ZILOG, INC. ]
