Z
ILOG
P R E L I M I N A R Y
Z16C32 IUSC
™
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z16C32
IUSC
™
I
NTEGRATED
U
NIVERSAL
S
ERIAL
C
ONTROLLER
FEATURES
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Two Full-Capacity 20 MHz DMA Channels, Each with
32-Bit Addressing and 16-Bit Data Transfers.
DMA Modes Include Single Buffer, Pipelined, Array-
Chained and Linked-Array Chained.
Ring Buffer Feature Supports Circular Queue of Buffers
in Memory.
Linked Frame Status Transfer Feature Writes Status
Information for Received Frames and Reads Control
Information for Transmit Frames to the DMA Channel’s
Array or Linked List to Significantly Simplify Processing
Frame Status and Control Information.
Programmable Throttling of DMA Bus Occupancy in
Burst Mode with Bus Occupancy Time Limitation.
0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud
Rate Generators and a Digital Phase-Locked Loop for
Clock Recovery.
32-Byte Data FIFOs for Receiver and Transmitter
Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth
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HDLC/SDLC Mode with 8-Bit Address Compare;
Extended Address Field Option; 16- or 32-Bit CRC;
Programmable Idle Line Condition; Optional Preamble
Transmission and Loop Mode. Selectable Number of
Flags Between Back-to-Back Frames.
Byte Oriented Synchronous Mode with One-to-Eight
Bits/Character; Programmable Sync and Idle Line
Conditions; Optional Receive Sync Stripping; Optional
Preamble Transmission; 16- or 32-Bit CRC; Transmit-
to-Receive Slaving (for X.21).
External Character Sync Mode for Receive
Transparent Bisync Mode with EBCDIC or ASCII
Character Code; Automatic CRC Handling;
Programmable Idle Line Condition; Optional Preamble
Transmission; Automatic Recognition of DLE, SYN,
SOH, ITX, ETX, ETB, EOT, ENQ and ITB.
Flexible Bus Interface for Direct Connection to Most
Microprocessors; User Programmable for 8 or 16 Bits
Wide. Directly Supports 680X0 Family or 8X86 Family
Bus Interfaces.
Receive and Transmit Time Slot Assigners for ISDN,
T1 and E1 (CEPT) Applications.
8-Bit General-Purpose Port with Transition Detection
Low Power CMOS
68-Pin PLCC Package
Electronic Programmer's Manual Support Tool and
Software Drivers are Available.
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Multiprotocol Operation Under Program Control with
Independent Mode Selection for Receiver and
Transmitter.
Async Mode with One-to-Eight Bits/Character, 1/16 to
Two Stop Bits/Character in 1/16 Bit Increments; 16x,
32x, or 64x Oversampling; Break Detect and
Generation; Odd, Even, Mark, Space or No Parity and
Framing Error Detection. Supports 9-Bit and MIL-STD-
1553B Protocols.
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GENERAL DESCRIPTION
The Z16C32 IUSC
™
(Integrated Universal Serial Controller)
is a multiprotocol datacommunications device with on-
chip dual-channel DMA. The integration of a high-speed
serial communications channel with high-performance
DMA facilitates higher data throughput than can be
achieved with discrete serial/DMA chip combinations.
PS97USC0200
1
ZILOG [ ZILOG, INC. ]
