Z8018x Family
MPU User Manual
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Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Logical Address Mapping Examples . . . . . . . . . . . . . . . . . 55
Physical Address Transition . . . . . . . . . . . . . . . . . . . . . . . 56
MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I/O Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Logical Memory Organization . . . . . . . . . . . . . . . . . . . . . 58
Logical Space Configuration . . . . . . . . . . . . . . . . . . . . . . . 59
Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . 64
Physical Address Generation 2 . . . . . . . . . . . . . . . . . . . . . 64
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TRAP Timing Diagram -2nd Op Code Undefined . . . . . . 71
TRAP Timing - 3rd Op Code Undefined . . . . . . . . . . . . . 72
NMI Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
INT0 Mode 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . 76
INT0 Mode 1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . 77
INT0 Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
INT0 Mode 2 Vector Acquisition . . . . . . . . . . . . . . . . . . . 79
INT0 Interrupt Mode 2 Timing Diagram . . . . . . . . . . . . . 80
INT1, INT2 Vector Acquisition . . . . . . . . . . . . . . . . . . . . 81
RETI Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 84
INT1, INT2 and Internal Interrupts Timing Diagram . . . . 86
Refresh Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . 87
DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DMA Timing Diagram-CYCLE STEAL Mode . . . . . . . 106
CPU Operation and DMA Operation DREQ0
is Programmed for Level-Sense . . . . . . . . . . . . . . . . . . . 107
Figure 48. CPU Operation and DMA Operation DREQ0
is Programmed for Edge-Sense . . . . . . . . . . . . . . . . . . . . 108
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
