Z8018x Family
MPU User Manual
ix
List of Figures
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Op Code Fetch (without Wait State) Timing Diagram . . . .19
Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Memory Read/Write (without Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Memory Read/Write (with Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Bus Exchange Timing During CPU Internal Operation . . .27
WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Memory and I/O Wait State Insertion
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
UM005001-ZMP0400