Z86129/130/131
NTSC Line 21 Decoder
PRELIMINARY
PIN DESCRIPTIONS
Inputs
VIDEO (Pin 7).
Composite NTSC video input, 1.0V p-p
(nom), band limited to 600 kHz. Circuit will operate with
signal variation between 0.7-1.4V p-p. The polarity is sync
tips negative. This signal pin should be AC coupled
through a 0.1
µF
capacitor and driven by a source
impedance of 470 ohms or less.
HIN (Pin 5).
Horizontal sync input at CMOS levels. When
the device is used in the VIDEO LOCK mode, this signal
pulls the on-chip VCO within the proper range. The circuit
uses the frequency of this signal which must be within
±3%
Fh but can be of either polarity. When used in the H LOCK
mode, the VCO phase locks to the rising edge of this
signal. The HPOL bit of the H Position register can be set
to operate with either polarity of input signal. This is usually
the H Flyback signal. The timing difference between HIN
rising edge and the leading edge of composite sync (of
VIDEO input) is one of the factors which will affect the
horizontal position of the display. Any shift resulting from
the timing of this signal can be compensated for with the
horizontal timing value in H Position Register.
SMS (Pin 6).
Mode select pin for the Serial Control Port.
When this input is at a CMOS High state (1) the Serial
Control Port will operate in the SPI mode. When the input
is Low (0), the Serial Control Port will operate in the I
2
C
slave mode. In SPI mode, the SEN pin must be tied High.
(See Reset Operation section.)
SEN (Pin 4).
Enable signal for the SPI mode operation of
the Serial Control Port. When this pin is Low (0), the SPI
port is disabled and the SDO pin is in the high-impedance
state. Transitions on the SCK and SDA pins are ignored.
SPI mode operation is enabled when SMS is High (1).
SCK (Pin 15).
Input pin for serial clock signal from the
master control device. In I
2
C mode operation the clock rate
is expected to be within I
2
C limits. In SPI mode, the
maximum clock frequency is 10 MHz.
Reset Operation.
When the SMS and SEN pins are both
in the Low (0) state, the part will be in the Reset state.
Therefore, in the I
2
C mode the SEN pin can be used as an
NReset input. When SPI mode is used, if three wire
operation is desired, both SMS and SEN can be tied
together and used as the NReset input. In either mode,
NReset must be held Low (0) for at least 100 ns.
Input/Output
VIN/INTRO (Pin 13).
In external (EXT) vertical lock mode
of operation, the internal vertical sync circuits will lock to
the VIN input signal applied at this pin. The part will lock to
the rising or falling edge of the signal in accordance with
the setting of the V Polarity command. The default is rising
edge. The VIN pulse must be at least 2 lines wide.
In INTRO Mode, when configured for internal vertical
synchronization, this pin will be an output pin providing an
interrupt signal to the master control device in accordance
with the settings in the Interrupt Mask Register.
SDA (Pin 14).
When the Serial Control Port has been set
to I
2
C mode operation, this pin serves as the bidirectional
data line for sending and receiving serial data. In SPI mode
operation it operates as serial data input. SPI mode output
data is available on the SDO pin.
Outputs
SDO (Pin 16).
Provides the serial data output when SPI
mode communications have been selected. This pin is not
used in I
2
C mode operation.
Box (Pin 17*).
Black box keying output is an active High,
CMOS level signal used to key in the black box in the
captions/text displays. This output will be in the high-
impedance state when the background attribute has been
set to semi-transparent (*Z86129 only).
RED, GREEN, BLUE (Pins 2*, 3*, 18*).
Positive acting
CMOS levels signals (*Z86129 only).
Color Mode: Red, Green and Blue character video outputs
for use in a color receiver.
s
Mono Mode: All three outputs carry the character
luminance information.
Notes:
The selection of Color/Mono Mode is user
controlled in bit D1 of the Configuration Register
(Address=00h). (See Internal Registers section.).
6
DS96TEL0200
ZILOG [ ZILOG, INC. ]
