Z86E30/E31/E40
Z8 4K OTP Microcontroller
allel I/O with or without handshake, and address/data bus
for interfacing external memory.
Notes:
All Signals with a preceding front slash, "/", are
active Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Zilog
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
(E40 Only)
VCC
Output Input
GND
XTAL /AS /DS R//W /RESET
Port 3
Machine Timing
&
Instruction Control
RESET
WDT POR
,
Counter/
Timers (2)
ALU
FLAGS
Interrupt
Control
Register
Pointer
Register File
Program
Counter
OTP
Two Analog
Comparators
Port 2
Port 0
Port 1
4
I/O
(Bit Programmable)
4
8
Address/Data or I/O
(Byte Programmable)
(E40 Only)
Address or I/O
(Nibble Programmable)
Figure 1. Z86E30/E31/E40 Functional Block Diagram
2
PRELIMINARY
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
