Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Zilog
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
Table 3. Control Register Reset Values
Reset Condition
tion. The POR time allows V and the oscillator circuit to
CC
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the five
following conditions:
Addr Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF SPL
FE GPR
FD RP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
■ Power bad to power good status
■ Stop-Mode Recovery
FC FLAGS U U U U U U U U
FB IMR
FA IRQ
0
U U U U U U U
U U
0
0
0
0
0
0 IRQ3 is used
for positive
edge
■ WDT time-out
■ WDT time-out (in HALT Mode)
■ WDT time-out (in STOP Mode)
detection
F9 IPR
U U U U U U U U
F8* P01M U U U
0
U U
0
0
1
1
F7* P3M
F6* P2M
U U U U U U
0 P2 open-drain
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
1
1
1
1
1
1
1 Inputs after
reset
F5 PRE0 U U U U U U U
0
F4 T0
U U U U U U U U
F3 PRE1 U U U U U U
0
0
F2 T1
F1 TMR
Notes:
U U U U U U U U
0
0
0
0
0
0
0
0
*Registers are not reset after a STOP-Mode Recovery using P27
pin. A subsequent reset will cause these control registers to be
reconfigured as shown in Table 4 and the user must avoid bus
contention on the port pins or it may affect device reliability.
14
P R E L I M I N A R Y
DS97LVO0901
ZILOG [ ZILOG, INC. ]
