P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z89321/371/391
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSORS
FEATURES
Device
Z89321
Z89371
Z89391
Note:
*External
s
1
DSP ROM
(KW)
4
OTP
(KW)
4
DSP RAM
Lines
512
512
512
MIPS
(Max)
24
16
24
Device
Z89321
Z89371
Z89391
40-Pin
DIP
X
X
44-Pin
PLCC
X
X
44-Pin
QFP
X
X
84-Pin
PLCC
64*
X
Note:
*General-Purpose
0
°
C to +70
°
C Standard Temperature Range
-40
°
C to +85
°
C Extended Temperature Range
4.5- to 5.5-Volt Operating Range
On-Board Peripherals
s
s
Dual 8/16-Bit CODEC Interface Capable of up to
10 Mbps
m
-Law Compression Option
(Decompression is Performed in Software)
16-Bit I/O Bus (Tri-Stated)
Three I/O Address Pins (Latched Outputs)
Wait-State Generator
Three Vectored Interrupts
13-Bit General-Purpose Timer
DSP Core
s
s
s
s
s
s
24 MIPS @ 24 MHz Maximum, 16-Bit Fixed Point DSP
s
41.7 ns Minimum Instruction Cycle Time
s
Six-Level Hardware Stack
s
Six Register Address Pointers
s
Optimized Instruction Set (30 Instructions)
s
GENERAL DESCRIPTION
The Z893XX products are high-performance Digital Signal
Processors (DSPs) with a modified Harvard-type architec-
ture featuring separate program and data memory. The de-
sign has been optimized for processing power while mini-
mizing silicon space.
The single-cycle instruction execution and bus structure
promotes efficient algorithm execution, while the six regis-
ter pointers provide circular buffering capabilities and dual
operand fetching.
Three vectored interrupts are complemented by a six-level
stack, and the CODEC interface allows high-speed trans-
fer rates to accommodate digital audio and voice data.
A dedicated Counter/Timer provides the necessary timing
signals for the CODEC interface, and an additional 13-bit
timer is available for general-purpose use.
DS97DSP0100
PRELIMINARY
1
ZILOG [ ZILOG, INC. ]
