欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F021APB020EC 参数 Datasheet PDF下载

Z8F021APB020EC图片预览
型号: Z8F021APB020EC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采! XP -R 4K系列高性能8位微控制器 [Z8 Encore! XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F021APB020EC的Datasheet PDF文件第60页浏览型号Z8F021APB020EC的Datasheet PDF文件第61页浏览型号Z8F021APB020EC的Datasheet PDF文件第62页浏览型号Z8F021APB020EC的Datasheet PDF文件第63页浏览型号Z8F021APB020EC的Datasheet PDF文件第65页浏览型号Z8F021APB020EC的Datasheet PDF文件第66页浏览型号Z8F021APB020EC的Datasheet PDF文件第67页浏览型号Z8F021APB020EC的Datasheet PDF文件第68页  
Z8 Encore! XP® 4K Series  
Product Specification  
45  
pin during STOP mode do not initiate STOP Mode Recovery.  
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on  
this pin during STOP mode initiates STOP Mode Recovery.  
Port A–D Pull-up Enable Sub-Registers  
The Port A–D Pull-up Enable sub-register (Table 25) is accessed through the Port A–D  
Control register by writing 06Hto the Port A–D Address register. Setting the bits in the  
Port A–D Pull-up Enable sub-registers enables a weak internal resistive pull-up on the  
specified Port pins.  
Table 25. Port A–D Pull-Up Enable Sub-Registers (PxPUE)  
BITS  
7
6
5
4
3
2
1
0
PPUE7  
PPUE6  
PPUE5  
PPUE4  
PPUE3  
PPUE2  
PPUE1  
PPUE0  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If 06H in Port AD Address Register, accessible through the Port AD Control Register  
ADDR  
PPUE[7:0]—Port Pull-up Enabled  
0 = The weak pull-up on the Port pin is disabled.  
1 = The weak pull-up on the Port pin is enabled.  
Port A–D Alternate Function Set 1 Sub-Registers  
The Port A–D Alternate Function Set1 sub-register (Table 26) is accessed through the Port  
A–D Control register by writing 07Hto the Port A–D Address register. The Alternate  
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate  
Functions selected by setting or clearing bits of this register are defined in GPIO Alternate  
Functions on page 33.  
Alternate function selection on port pins must also be enabled as decribed in Port A–D  
Note:  
Alternate Function Sub-Registers on page 42.  
Table 26. Port A–D Alternate Function Set 1 Sub-Registers (PxAFS1)  
BITS  
7
6
5
4
3
2
1
0
PAFS17  
PAFS16  
PAFS15  
PAFS14  
PAFS13  
PAFS12  
PAFS11  
PAFS10  
FIELD  
RESET  
R/W  
00H (all ports of 20/28 pin devices); 04H (Port A of 8-pin device)  
R/W R/W R/W R/W R/W R/W  
R/W  
R/W  
If 07H in Port A–D Address Register, accessible through the Port A–D Control Register  
ADDR  
PAFS1[7:0]—Port Alternate Function Set 1  
0 = Port Alternate Function selected as defined in Tables 15 and 16 in the GPIO Alternate  
PS022815-0206  
General-Purpose I/O