Z8 Encore! XP
®
4K Series
Product Specification
122
6. Add the gain correction factor to the original offset corrected value.
#5 MSB
+
#1 MSB
=
#6 MSB
#6 LSB
7. Shift the result to the right, using the sign bit determined in step #1 above. This will
allow for the detection of computational overflow.
S->
Output Data
The following is the output format of the corrected ADC value.
MSB
s v b a 9 8 7 6
#5 LSB
#1 LSB
#6 MSB
#6 LSB
LSB
5 4 3 2 1 0 - -
The overflow bit in the corrected output indicates that the computed value was greater
than the maximum logical value (+1023) or less than the minimum logical value (-1024).
Unlike the hardware overflow bit, this is not a simple binary flag. For a normal sample
(non-overflow), the sign and the overflow bit will match. If the sign bit and overflow bit
do not match, a computational overflow has occurred.
Input Buffer Stage
Many applications require the measurement of an input voltage source with a high output
impedance. This ADC provides a buffered input for such situations. The drawback of the
buffered input is a limitation of the input range. When using unity gain buffered mode, the
input signal must be prevented from coming too close to either V
SS
or V
DD
. See
for details.
This condition applies only to the input voltage level (with respect to ground) of each dif-
ferential input signal. The actual differential input voltage magnitude may be less than 300
mV.
The input range of the unbuffered ADC swings from V
SS
to V
DD
. Input signals smaller
than 300 mV must use the unbuffered input mode. If these signals do not contain low out-
put impedances, they might require off-chip buffering.
PS022815-0206
Analog-to-Digital Converter
ZILOG [ ZILOG, INC. ]
