Z8 Encore! XP® 4K Series
Product Specification
151
Trim Bit Data Register
The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim
option bits.
Table 88. Trim Bit Data Register (TRMDR)
BITS
7
6
5
4
3
2
1
0
TRMDR - Trim Bit Data
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF7H
ADDR
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000Hand 0001Hare reserved
for the user-programmable Flash option bits.
Flash Program Memory Address 0000H
Table 89. Flash Option Bits at Program Memory Address 0000H
BITS
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
OSC_SEL[1:0]
VBO_AO
FRP
Reserved
FWP
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watch-Dog Timer Reset
0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watch-Dog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watch-Dog Timer Always On
0 = Watch-Dog Timer is automatically enabled upon application of system power. Watch-
Dog Timer can not be disabled.
1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This set-
ting is the default for unprogrammed (erased) Flash.
PS022815-0206
Flash Option Bits
ZILOG [ ZILOG, INC. ]
