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Z8F041ASH020SC 参数 Datasheet PDF下载

Z8F041ASH020SC图片预览
型号: Z8F041ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R 4K系列高性能8位微控制器 [Z8 Encore XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® 4K Series  
Product Specification  
177  
Step Instruction (10H)—The Step Instruction command steps one assembly instruction  
at the current Program Counter (PC) location. If the device is not in DEBUG mode or the  
Flash Read Protect Option bit is enabled, the OCD ignores this command.  
DBG 10H  
Stuff Instruction (11H)—The Stuff Instruction command steps one assembly instruction  
and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the  
instruction are read from Program Memory. This command is useful for stepping over in-  
structions where the first byte of the instruction has been overwritten by a Breakpoint. If  
the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, the  
OCD ignores this command.  
DBG 11H  
DBG opcode[7:0]  
Execute Instruction (12H)—The Execute Instruction command allows sending an en-  
tire instruction to be executed to the eZ8 CPU. This command can also step over Break-  
points. The number of bytes to send for the instruction depends on the opcode. If the device  
is not in DEBUG mode or the Flash Read Protect Option bit is enabled, this command  
reads and discards one byte.  
DBG 12H  
DBG 1-5 byte opcode  
On-Chip Debugger Control Register Definitions  
OCD Control Register  
The OCD Control register controls the state of the On-Chip Debugger. This register is  
used to enter or exit DEBUG mode and to enable the BRKinstruction. It can also reset the  
Z8 Encore! XP® 4K Series device.  
A reset and stop function can be achieved by writing 81Hto this register. A reset and go  
function can be achieved by writing 41Hto this register. If the device is in DEBUG mode,  
a run function can be implemented by writing 40H to this register.  
.
Table 109. OCD Control Register (OCDCTL)  
BITS  
7
6
5
4
3
2
1
0
DBGMODE BRKEN DBGACK  
Reserved  
RST  
FIELD  
RESET  
R/W  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R
R
R
R
R/W  
DBGMODE—Debug Mode  
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU  
PS022815-0206  
On-Chip Debugger