Z8 Encore! XP
®
4K Series
Product Specification
50
Interrupt Controller
Overview
The interrupt controller on the Z8 Encore! XP
®
4K Series products prioritizes the interrupt
requests from the on-chip peripherals and the GPIO port pins. The features of the interrupt
controller include the following:
•
•
•
•
20 unique interrupt vectors:
–
12 GPIO port pin interrupt sources (two are shared)
–
10 on-chip peripheral interrupt sources (two are shared)
Flexible GPIO interrupts
–
Eight selectable rising and falling edge GPIO interrupts
–
Four dual-edge interrupts
Three levels of individually programmable interrupt priority
Watch-Dog Timer and LVD can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. Refer to the
eZ8 CPU User Manual
for
more information regarding interrupt servicing by the eZ8 CPU. The
eZ8 CPU User Man-
ual
is available for download at
www.zilog.com.
Interrupt Vector Listing
lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most significant byte (MSB) at the even Program Memory address and the
least significant byte (LSB) at the following odd Program Memory address.
Note:
Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is
unavailable on devices not containing an ADC.
PS022815-0206
Interrupt Controller
ZILOG [ ZILOG, INC. ]
