Z8 Encore!® 64K Series
Product Specification
140
Architecture
Figure 27 illustrates the architecture of the I2C Controller.
SDA
SCL
Shift
ISHIFT
Load
2
I CDATA
Baud Rate Generator
2
Receive
I CBRH
2
I CBRL
Tx/Rx State Machine
2
2
I CSTAT
I CCTL
Register Bus
2
I C Interrupt
2
Figure 27. I C Controller Block Diagram
Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
•
•
Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
PS019915-1005
I2C Controller