Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
130
DMA_ADC Control Register
The DMA_ADC Control register enables and sets options (DMA enable and interrupt
enable) for ADC operation.
Table 78. DMA_ADC Control Register (DMAACTL)
BITS
FIELD
RESET
R/W
ADDR
7
DAEN
0
R/W
6
IRQEN
0
R/W
5
Reserved
0
R/W
4
3
2
ADC_IN
1
0
0
R/W
FBEH
0
R/W
0
R/W
0
R/W
0
R/W
DAEN—DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
IRQEN—Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC Analog
Input specified by the ADC_IN field.
Reserved
These bits are reserved and must be 0.
ADC_IN—ADC Analog Input Number
These bits set the number of ADC Analog Inputs to be used in the continuous update (data
conversion followed by DMA data transfer). The conversion always begins with ADC
Analog Input 0 and then progresses sequentially through the other selected ADC Analog
Inputs.
0000 = ADC Analog Input 0 updated.
0001 = ADC Analog Inputs 0-1 updated.
0010 = ADC Analog Inputs 0-2 updated.
0011 = ADC Analog Inputs 0-3 updated.
0100 = ADC Analog Inputs 0-4 updated.
0101 = ADC Analog Inputs 0-5 updated.
0110 = ADC Analog Inputs 0-6 updated.
0111 = ADC Analog Inputs 0-7 updated.
1000 = ADC Analog Inputs 0-8 updated.
1001 = ADC Analog Inputs 0-9 updated.
1010 = ADC Analog Inputs 0-10 updated.
1011 = ADC Analog Inputs 0-11 updated.
1100-1111 = Reserved.
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
