Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
135
–
–
–
Set
CONT
to 1 to select continuous conversion.
Write to
VREF
to enable or disable the internal voltage reference generator.
Set
CEN
to 1 to start the conversions.
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
–
CEN
resets to 0 to indicate the first conversion is complete.
CEN
remains 0 for all
subsequent conversions in continuous operation.
– An interrupt request is sent to the Interrupt Controller to indicate the
first
conversion is complete. An interrupt request is not sent for subsequent
conversions in continuous operation.
4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0],
ADCD_L[7:6]} every 256 system clock cycles.
5. To disable continuous conversion, clear the
CONT
bit in the ADC Control register
to 0.
DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC includ-
ing analog input selection and conversion enable. For more information on the DMA and
configuring for ADC operations refer to the
Direct Memory Access Controller
chapter.
ADC Control Register Definitions
ADC Control Register
The ADC Control register selects the analog input channel and initiates the analog-to-dig-
ital conversion.
Table 80. ADC Control Register (ADCCTL)
BITS
FIELD
RESET
R/W
ADDR
7
CEN
0
R/W
6
Reserved
0
R/W
5
VREF
0
R/W
4
CONT
0
R/W
F70H
3
2
1
0
ANAIN[3:0]
0000
R/W
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
PS017610-0404
Analog-to-Digital Converter
ZILOG [ ZILOG, INC. ]
