Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!
®
29
External Pin Reset
The RESET pin has a Schmitt-triggered input and an internal pull-up. Once the RESET
pin is asserted, the device progresses through the Short Reset sequence. While the RESET
input pin is asserted Low, the Z8F640x family device continues to be held in the Reset
state. If the RESET pin is held Low beyond the Short Reset time-out, the device exits the
Reset state immediately following RESET pin deassertion. Following a Short Reset initi-
ated by the external RESET pin, the
EXT
status bit in the Watch-Dog Timer Control
(WDTCTL) register is set to 1.
Stop Mode Recovery
Stop mode is entered by execution of a
STOP
instruction by the eZ8 CPU. Refer to the
Low-Power Modes
chapter for detailed Stop mode information. During Stop Mode
Recovery, the Z8F640x family device is held in reset for 514 cycles of the Watch-Dog
Timer oscillator followed by 16 cycles of the system clock (crystal oscillator). Stop Mode
Recovery does not affect any values in the Register File, including the Stack Pointer, Reg-
ister Pointer, Flags and general-purpose RAM.
0002H
and
0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop Mode Recovery, the
STOP
bit in the Watch-Dog Timer Con-
trol Register is set to 1. Table 9 lists the Stop Mode Recovery sources and resulting
actions. The text following provides more detailed information on each of the Stop Mode
Recovery sources.
Table 9. Stop Mode Recovery Sources and Resulting Action
Operating Mode
Stop mode
Stop Mode Recovery Source
Watch-Dog Timer time-out
when configured for Reset
Watch-Dog Timer time-out
when configured for interrupt
Action
Stop Mode Recovery
Stop Mode Recovery followed by interrupt (if
interrupts are enabled)
Data transition on any GPIO Port pin
Stop Mode Recovery
enabled as a Stop Mode Recovery source
Stop Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during Stop mode, the Z8F640x family device under-
goes a STOP Mode Recovery sequence. In the Watch-Dog Timer Control register, the
WDT
and STOP bits are set to 1. If the Watch-Dog Timer is configured to generate an inter-
rupt upon time-out and the device is configured to respond to interrupts, the Z8F640x fam-
ily device services the Watch-Dog Timer interrupt request following the normal Stop
Mode Recovery sequence.
PS017610-0404
Reset and Stop Mode Recovery
ZILOG [ ZILOG, INC. ]
