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51
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 27 and 28) form a priority encoded
enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting
bits in each register. Table 26 describes the priority control for IRQ0.
Table 26. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
Nominal
High
where
x
indicates the register bits from 0 through 7.
Table 27. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
ADDR
7
T2ENH
0
R/W
6
T1ENH
0
R/W
5
T0ENH
0
R/W
4
U0RENH
0
R/W
FC1H
3
U0TENH
0
R/W
2
I2CENH
0
R/W
1
SPIENH
0
R/W
0
ADCENH
0
R/W
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I
2
C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
PS017610-0404
Interrupt Controller
ZILOG [ ZILOG, INC. ]
