Z8 Encore!® Motor Control Flash MCUs
Product Specification
208
[1]
DIV4
DIV4
0
1
Clock is not divided
System Clock is divided by 4 for ADC Clock
[2]
DIV8
DIV8
0
1
Clock is not divided
System Clock is divided by 8 for ADC Clock
[3]
DIV16
DIV16
0
Clock is not divided
1
System Clock is divided by 16 for ADC Clock
Reserved - must be 0.
[7:4]
0H
ADC Timer Capture High Byte Register
The high byte of the ADC Timer Capture Register, shown in Table 111, contains the upper
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture High Byte Regis-
ter is Read-Only.
Table 111. ADC Timer Capture High Byte Register (ADCTCAP_H)
BITS
7
6
5
4
3
2
1
0
ADCTCAPH
FIELD
RESET
R/W
X
R
F08H
ADDR
Bit
Value
(H)
Description
Position
[7:0]
00H–FFH ADC Timer Capture Count High Byte
The timer count is held in the data registers until the next ADC conversion is
started.
ADC Timer Capture Low Byte Register
The low byte of the ADC Timer Capture Register, shown in Table 112, contains the lower
eight bits of the ADC Timer 0 count. Access to the ADC Timer Capture Low Byte Regis-
ter is Read-Only.
Analog-to-Digital Converter
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
