Z8FMC16100 Series Flash MCU
Product Specification
57
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) Register, shown in Table 31, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 31. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
7
I2CI
6
5
4
PBI
3
2
1
0
Reserved
PC0I
PA73I
PA62I
PA51I
PA40I
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
FC3H
ADDR
Bit
Value
(H)
Description
Position
[7]
I2C Interrupt Request
No interrupt request is pending for I2C.
I2CI
0
1
An interrupt request from I2C is awaiting service.
[5]
PC0 Interrupt Request — Logic in the Port C GPIO module selects either the
rising or falling edge.
PC0I
0
1
No interrupt request is pending for PC0.
An interrupt request from PC0 is awaiting service.
[4]
PB3 – PB0 Interrupt Request
PBI
0
1
No interrupt request is pending for any PB3 – PB0.
An interrupt request from PB3 – PB0 is awaiting service.
[3]
PA7 or PA3 Interrupt Request — Logic in the Port A GPIO module selects either
PA7 or PA3 and either rising or falling edge.
PA73I
0
1
No interrupt request is pending for PA7 or PA3
An interrupt request from PA7 or PA3 is awaiting service.
[2]
PA6 or PA2 Interrupt Request — Logic in the Port A GPIO module selects either
PA6 or PA2 and either rising or falling edge.
PA62I
0
1
No interrupt request is pending for PA6 or PA2
An interrupt request from PA6 or PA2 is awaiting service.
PS024604-1005
P R E L I M I N A R Y
Interrupt Request 1 Register
ZILOG [ ZILOG, INC. ]
