Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Notes:
All Signals with a preceding front slash, “/” are ac-
tive Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only). Alternatively, an overslash
may be used to signify active Low, for example WR
Zilog
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
/BUSREQ
/RESET
/BUSACK
/MREQ
EXTAL
/RFSH
/HALT
/WAIT
IORQ
XTAL
INT0
INT1
/RD
Ø
Timing
Generator
Bus State Control
CPU
Interrupt
A18/TOUT
16-bit
Programmable
Reload Timers
(2)
/DREQ1
DMAC
S
(2)
TEND1
TXS
RXS/CTS1
CKS
Clocked
Serial I/O
Port
Address Bus (16-Bit)
Data Bus (8-Bit)
TXA0
Asynchronous
SCI
(Channel 0)
CKA0, /DREQ0
RXA0
/RTS0
/CTS0
/DCD0
TXA1
Asynchronous
SCI
(Channel 1)
CKA1, /TEND0
RXA1
MMU
Address
Buffer
Data
Buffer
VCC
VSS
A19-A0
D7-D0
Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram
1-2
PRELIMINARY
DS971800401
INT2
/NMI
/WR
/M1
ST
E
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