Zilog
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Table 2. Pin Status During RESET BUSACK and SLEEP
Pin Number and Package Type
QFP
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PLCC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DIP
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Default
Function
/RTS0
/CTS0
/DCD0
TXA0
RXA0
CKA0
NC
TXA1
TEST
RXA1
CKA1
TXS
RXS
CKS
/DREQ1
/TEND1
/HALT
NC
NC
/RFSH
/IORQ
/MREQ
E
/M1
/WR
/RD
PHI
V
SS
V
SS
2
3
4
5
6
7
XTAL
NC
EXTAL
/WAIT
/BUSACK
/BUSREQ
/RESET
Secondary
Function
RESET
1
IN
IN
1
IN
3T
1
IN
3T
1
IN
3T
IN
1
1
Pin Status
BUSACK
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
I/O
3T
OUT
1
1
SLEEP
1
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
I/O
IN
1
0
/DREQ0
/TEND0
/CTS1
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
57
58
59
60
61
62
63
64
1
1
1
1
0
1
1
1
OUT
GND
GND
OUT
IN
IN
1
IN
IN
OUT
3T
3T
OUT
1
3T
3T
OUT
GND
GND
OUT
IN
IN
OUT
IN
IN
OUT
1
1
OUT
1
1
1
OUT
GND
GND
OUT
IN
IN
OUT
IN
IN
DS971800401
PRELIMINARY
1-9
ZILOG [ ZILOG, INC. ]
