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U62256AS2C10G1 参数 Datasheet PDF下载

U62256AS2C10G1图片预览
型号: U62256AS2C10G1
PDF下载: 下载PDF文件 查看货源
内容描述: 标准的32K ×8 SRAM [STANDARD 32K X 8 SRAM]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 164 K
品牌: ZMD [ Zentrum Mikroelektronik Dresden AG ]
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U62256A
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
Output Enable Access Time to Data Valid
E HIGH to Output in High-Z
G HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
Symbol
Alt.
t
RC
t
AA
t
ACE
t
OE
t
HZCE
t
HZOE
t
LZCE
t
LZOE
t
OH
IEC
t
cR
t
a(A)
t
a(E)
t
a(G)
t
dis(E)
t
dis(G)
t
en(E)
t
en(G)
t
v(A)
5
0
5
Min.
70
70
70
35
25
25
5
0
5
07
Max.
Min.
100
100
100
45
35
35
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Pulse Width Setup Time
Address Setup Time
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
Data Hold Time
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
t
AW
t
CW
t
CW
t
DS
t
DH
t
AH
t
HZWE
t
HZOE
t
LZWE
t
LZOE
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(A-WH)
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
dis(W)
t
dis(G)
t
en(W)
t
en(G)
0
0
Min.
70
55
55
0
65
65
65
30
0
0
07
Max.
Min.
100
70
70
0
80
80
80
35
0
0
25
25
0
0
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
ns
ns
ns
ns
April 20, 2004
5