U634H256
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = HIGH after STORE initiation)
t
cR
(29)
t
cR
(29)
Ai
E
DQi
Output
ADDRESS 1
t
w(E)SR
(34)
t
su(A)SR
(33)
High Impedance
VALID
(35)
ADDRESS 6
t
w(E)SR
(34)
t
h(A)SR
(35)
t
su(A)SR
(33)
t
dis(E)
(5)
t
d(E)S
(31)
VALID
t
dis(E)SR
(30)
t
d(E)R
(32)
t
h(A)SR
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = LOW after STORE initiation)
t
cR
(29)
Ai
E
DQi
Output
t
su(A)SR
(33)
ADDRESS 1
t
w(E)SR
(34)
t
h(A)SR
(35)
VALID
(33)
ADDRESS 6
t
h(A)SR
(35)
t
su(A)SR
t
d(E)S
(31)
VALID
t
dis(E)SR
(30)
t
d(E)R
(32)
High Impedance
u: If the chip enable pulse width is less then t
a(E)
(see READ cycle) but greater than or equal to t
w(E)SR
, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
April 21, 2004
9
ZMD [ Zentrum Mikroelektronik Dresden AG ]
