Datasheet
ZADCS1082/1042/1022 Family
1.5
Electrical Characteristics
1.5.1 General Parameters
(VDD = +2.7V to + 5.25V; f
SCLK
= 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); V
REF
= 2.500V applied to VREF pin;
q
OP
=
q
OPmin
…
q
OPmax
)
Parameter
DC Accuracy
Resolution
Relative Accuracy
No Missing Codes
Differential Nonlinearity
Offset Error
Gain Error
Gain Temperature Coefficient
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Small-Signal Bandwidth
Symbol Conditions
Min
Typ
10
Max
Unit
Bits
INL
NMC
DNL
ZADCS1082 / ZADCS1082V
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
10
ZADCS1082 / ZADCS1082V
ZADCS1042 / ZADCS1042V
ZADCS1022 / ZADCS1022V
±
0.5
±
0.5
±
0.25
±
0.4
LSB
Bits
±
0.4
±
2.0
±
2.0
LSB
LSB
LSB
ppm/°C
dB
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock)
SINAD
THD
SFDR
-3dB roll off
Ext. Clock = 3.3MHz, 2.5 clocks/ acquisi-
tion
Ext. Clock = 3.3MHz, 10 clocks/ conver-
sion
Int. Clock = 3.3MHz +/- 12% tolerance
Aperture Delay
Aperture Jitter
External Clock Frequency
Internal Clock Frequency
0.1
2.81
3.3
2.75
30
< 50
3.3
3.58
Up to the 5
th
harmonic
74
3.8
61
-72
dB
dB
MHz
Conversion Rate
Sampling Time
(= Track/Hold Acquisition Time)
Conversion Time
t
ACQ
t
CONV
0.758
3.03
3.50
µs
µs
µs
ns
ps
MHz
MHz
Analog Inputs
Input Voltage Range, Single-
Ended and Differential
Input Capacitance
Unipolar, COM = 0V
Bipolar, COM = VREF/2
0 to VREF
±
VREF / 2
16
V
pF
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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ZMD [ Zentrum Mikroelektronik Dresden AG ]
