楼主：跪求：IDE硬盘接口方面的资料
作者：advanceli  2005-10-12 12:12:00

我在想采用周立功的ARM扩展出一个IDE硬盘接口，网上搜索有关方面的资料，或者只是介绍IDE的定义或者就扯到配电脑上，希望能有个比较全面的资料，比如读写时序，引脚定义等等。

我在周立功的树上看到有关的介绍，但是比较粗略，我是新手。。。

（1）它在书中谈到某些信号只对“16位系统”有效，那么ARM这个32位的处理器呢？

（2）寄存器的读写时序中提到了模式0～4的读写时间，这几个模式从何而来？有什么区别？

望大侠指教，不胜感激！！！

作者：advanceli  2005-10-12 12:13:00

Copies of this proposal may be purchased from:BSR X3.221

Global Engineering, 2805 McGaw St, Irvine, CA 92714X3T9.2/90-143

800-854-7179714-261-1455

working draft proposed American National

Standard for Information Systems -

ATA (AT Attachment)

Rev 3.2October 16, 1992

Secretariat

Computer and Business Equipment Manufacturers Association (CBEMA)

Abstract:This standard defines an integrated bus interface between disk

drives and host processors. It provides a common point of attachment for

systems manufacturers, system integrators, and suppliers of intelligent

peripherals.

draft proposed American National Standard

This is a draft proposed American National Standard of Accredited Standards

Committee X3.As such this is not a completed standard.The X3T9 Technical

Committee may modify this document as a result of comments received during

public review and its approval as a standard.

POINTS OF CONTACT:

John B. LohmeyerI. Dal Allan

Chairman X3T9.2Vice-Chairman X3T9.2

NCRENDL

1635 Aeroplaza Dr14426 Black Walnut Court

Colorado SpringsCO 80916SaratogaCA 95070

719-596-5795 x362408-867-6630

An electronic copy of this document is available from the SCSI Bulletin Board

(719-574-0424).

This document has been prepared according to the style guide of the ISO

(International Organization of Standards).

If this document was printed in a 2-up form directly from the printer, NOTEs

had to be adjusted to fit into a half-page, which may have resulted in an

imperfect representation of the format within the NOTE. This is most likely to

occur if a series of NOTEs are mixed in without any line separation.

ATA was forwarded in August 1991 from X3T9.2 to X3T9 for further processing as

an American National Standard.X3T9 authorized a letter ballot on forwarding

this document as a preliminary draft proposed American National Standard.

X3 authorized a Public Review of Rev 3.0 of the document as a draft proposed

American National Standard.

This revision reflects comments received during the 4-month Public Review, and

recommendations made by the ATA Working Group of X3T9.2. Amongst the technical

changes included herein that differ from the Rev 3.0 document are:

NOP:

Additional command

Multiword DMA:

Additional timing chart

Additions to Identify Drive

Additions to Set Features

SFF 44-pin:

Additional Annex

LBA (Logical Block Addressing):

Additional description

Additions to Identify Drive

Additions to Register descriptions

All changes from Rev 3.0 are marked in bold.

Foreword: This Foreword is not part of American National Standard X3.***-199x.

When the first IBM PC (Personal Computer) (tm) was introduced, there was no

hard disk capability for storage. Successive generations of product resulted

in the inclusion of a hard disk as the primary storage device. When the PC AT

(tm) was developed, a hard disk was the key to system performance, and the

controller interface became a de facto industry interface for the inclusion of

hard disks in PC ATs.

The price of desktop systems has declined rapidly because of the degree of

integration to reduce the number of components and interconnects required to

build a product. A natural outgrowth of this integration was the inclusion of

controller functionality into the hard disk.

In October 1988 a number of peripheral suppliers formed the Common Access

Method Committee to encourage an industry-wide effort to adopt a common

software interface to dispatch input/output requests to SCSI peripherals.

Although this was the primary objective, a secondary goal was to specify what

is known as the AT Attachment interface.

Suggestions for improvement of this standard will be welcome. They should be

sent to the Computer and Business Equipment Manufacturers Association, 311

First Street N.W., Suite 500, Washington, DC 20001.

This standard was processed and approved for submittal to ANSI by the

Accredited Standards Committee on Information Processing Systems, X3.

Committee approval of this standard does not necessarily imply that all

committee members voted for its approval. At the time it approved this

standard, the X3 Committee had the following members:

X3 Committee list goes here:

Subcommittee X3T9 on I/O interfaces, which reviewed this standard, had the

following members:

X3T9 Committee list goes here:

Task Group X3T9.2 on Lower-Level Interfaces, which completed the development

of this standard, had the following members:

X3T9.2 Committee list goes here:

The initial development work on this standard was done by the CAM Committee.

The membership of the CAM Committee consisted of the following organizations:

AdaptecData TechnologyNCR

AMDEastman KodakOlivetti

AppleEmulexQuantum

AT&T Bell LabsFujitsu uElectronicsScientific Micro Systems

CaliperFuture DomainSeagate

Cambrian SystemsHewlett PackardSony

Cipher DataIBMStorage Dimensions

Cirrus LogicImprimisSun Microsystems

Columbia DataInteractive SystemsSyquest Technology

CompuAddJVCSytron

Conner PeripheralsLMS OSDTrantor

Dell ComputerMaxtorWestern Digital

Digital EquipmentMicropolis

DPTMiniscribe

TABLE OF CONTENTS

1.Scope1

1.1Description of Clauses1

2.References1

3.General Description1

3.1Structure2

4.Definitions and Conventions2

4.1Definitions2

4.2Conventions3

5.Interface Cabling Requirements3

5.1Configuration3

5.2Addressing Considerations4

5.3DC Cable and Connector5

5.3.14-Pin Power5

5.3.23-Pin Power5

5.3.3Device Grounding6

5.4I/O Connector6

5.5I/O Cable6

6.Physical Interface7

6.1Signal Conventions7

6.2Signal Summary7

6.3Signal Descriptions9

6.3.1CS1FX- (Drive chip Select 0)9

6.3.2CS3FX- (Drive chip Select 1)9

6.3.3DA0-2 (Drive Address Bus)10

6.3.4DASP- (Drive Active/Drive 1 Present)10

6.3.5DD0-DD15 (Drive Data Bus)10

6.3.6DIOR- (Drive I/O Read)10

6.3.7DIOW- (Drive I/O Write)10

6.3.8DMACK- (DMA Acknowledge) (Optional)10

6.3.9DMARQ (DMA Request) (Optional)11

6.3.10INTRQ (Drive Interrupt)11

6.3.11IOCS16- (Drive 16-bit I/O)11

6.3.12IORDY (I/O Channel Ready) (Optional)12

6.3.13PDIAG- (Passed Diagnostics)12

6.3.14RESET- (Drive Reset)12

6.3.15SPSYNC:CSEL (Spindle Synchronization/Cable Select)

(Optional)12

6.3.15.1SPSYNC (Spindle Synchronization) (Optional)13

6.3.15.2CSEL (Cable Select) (Optional)13

7.Logical Interface14

7.1General14

7.1.1Bit Conventions14

7.1.2Environment14

7.2I/O Register Descriptions15

7.2.1Alternate Status Register16

7.2.2Command Register16

7.2.3Cylinder High Register16

7.2.4Cylinder Low Register17

7.2.5Data Register17

7.2.6Device Control Register17

7.2.7Drive Address Register17

7.2.8Drive/Head Register18

7.2.9Error Register18

7.2.10Features Register19

7.2.11Sector Count Register19

7.2.12Sector Number Register19

7.2.13Status Register19

8.Programming Requirements21

8.1Reset Response21

8.2Translate Mode22

8.3Power Conditions22

8.4Error Posting22

9.Command Descriptions23

9.1Acknowledge Media Change (Removable)25

9.2Boot - Post-Boot (Removable)25

9.3Boot - Pre-Boot (Removable)25

9.4Check Power Mode26

9.5Door Lock (Removable)26

9.6Door Unlock (Removable)26

9.7Execute Drive Diagnostic26

9.8Format Track27

9.9Identify Drive28

9.9.1Word 1: Number of cylinders29

9.9.2Word 3: Number of heads29

9.9.3Word 4: Number of unformatted bytes per track29

9.9.4Word 5: Number of unformatted bytes per sector30

9.9.5Word 6: Number of sectors per track30

9.9.6Word 10-19: Serial Number30

9.9.7Word 20: Buffer Type30

9.9.8Word 22: ECC bytes Available on Read/Write Long Commands30

9.9.9Word 23-26: Firmware Revision30

9.9.10Word 27-46: Model Number30

9.9.11Word 51:PIO data transfer cycle timing mode30

9.9.12Word 52:DMA data transfer cycle timing mode30

9.9.13Word 54:Number of current cylinders31

9.9.14Word 55:Number of current heads31

9.9.15Word 56:Number of current sectors per track31

9.9.16Word 57-58: Current capacity in sectors31

9.9.17Word 59: Multiple Sector Setting31

9.9.18Word 60-61: Total Number of User Addressable Sectors31

9.9.19Word 62: Single Word DMA Transfer31

9.9.20Word 63: Multiword DMA Transfer31

9.10Idle31

9.11Idle Immediate32

9.12Initialize Drive Parameters32

9.13NOP32

9.14Read Buffer32

9.15Read DMA33

9.16Read Long33

9.17Read Multiple Command33

9.18Read Sector(s)34

9.19Read Verify Sector(s)34

9.20Recalibrate35

9.21Seek35

9.22Set Features35

9.23Set Multiple Mode36

9.24Sleep36

9.25Standby37

9.26Standby Immediate37

9.27Write Buffer37

9.28Write DMA37

9.29Write Long37

9.30Write Multiple Command38

9.31Write Same38

9.32Write Sector(s)39

9.33Write Verify39

10.Protocol Overview39

10.1PIO Data In Commands40

10.1.1PIO Read Command40

10.1.2PIO Read Aborted Command40

10.2PIO Data Out Commands40

10.2.1PIO Write Command41

10.2.2PIO Write Aborted Command41

10.3Non-Data Commands41

10.4Miscellaneous Commands42

10.5DMA Data Transfer Commands (Optional)42

10.5.1Normal DMA Transfer43

10.5.2Aborted DMA Transfer43

10.5.3Aborted DMA Command43

11.Timing43

11.1Deskewing43

11.2Symbols43

11.3Terms44

11.4Data Transfers45

11.5Power On and Hard Reset48

FIGURES

FIGURE 5-1:ATA INTERFACE TO EMBEDDED BUS PERIPHERALS4

FIGURE 5-2:HOST BUS ADAPTER AND PERIPHERAL DEVICES4

FIGURE 5-3:ATA INTERFACE TO CONTROLLER AND PERIPHERAL DEVICES4

FIGURE 5-4:40-PIN CONNECTOR MOUNTING6

FIGURE 6-1:Cable Select14

FIGURE 11-1:PIO DATA TRANSFER TO/FROM DRIVE45

FIGURE 11-2:IORDY TIMING REQUIREMENTS46

FIGURE 11-3:SINGLE WORD DMA DATA TRANSFER46

FIGURE 11-4:MULTIWORD DMA DATA TRANSFER47

FIGURE 11-5:RESET SEQUENCE48

TABLES

TABLE 5-1:DC INTERFACE5

TABLE 5-2:DC INTERFACE5

TABLE 5-3:CABLE PARAMETERS7

TABLE 6-1:INTERFACE SIGNALS8

TABLE 6-2:INTERFACE SIGNALS DESCRIPTION9

TABLE 7-1:I/O PORT FUNCTIONS/SELECTION ADDRESSES16

TABLE 8-1:POWER CONDITIONS22

TABLE 8-2:REGISTER CONTENTS23

TABLE 9-1:COMMAND CODES AND PARAMETERS - Part 1 of 224

TABLE 9-1:COMMAND CODES AND PARAMETERS - Part 2 of 225

TABLE 9-2:DIAGNOSTIC CODES27

TABLE 9-4:SET FEATURE REGISTER DEFINITIONS35

TABLE C-1SIGNAL ASSIGNMENTS FOR ATA58

Information Processing Systems --

AT Attachment Interface

1. Scope

This standard defines the AT Attachment Interface.

The CAM Committee was formed in October, 1988 and the first working document

of the AT Attachment was introduced in March, 1989.

1.1Description of Clauses

Clause 1 contains the Scope and Purpose.

Clause 2 contains Referenced and Related International Standards.

Clause 3 contains the General Description.

Clause 4 contains the Glossary.

Clause 5 contains the electrical and mechanical characteristics; covering the

interface cabling requirements of the DC, data cables and connectors.

Clause 6 contains the signal descriptions of the AT Attachment Interface.

Clause 7 contains descriptions of the registers of the AT Attachment

Interface.

Clause 8 describes the programming requirements of the AT Attachment

Interface.

Clause 9 contains descriptions of the commands of the AT Attachment Interface.

Clause 10 contains an overview of the protocol of the AT Attachment Interface.

Clause 11 contains the interface timing diagrams.

Annex A is informative.

Annex B is informative.

Annex C is informative.

2. References

None.

3.General Description

The application environment for the AT Attachment Interface is any computer

which uses an AT Bus or 40-pin ATA interface.

The PC AT Bus (tm) is a widely used and implemented interface for which a

variety of peripherals have been manufactured. As a means of reducing size and

cost, a class of products has emerged which embed the controller functionality

in the drive. These new products utilize the AT Bus fixed disk interface

protocol, and a subset of the AT bus. Because of their compatibility with

existing AT hardware and software this interface quickly became a de facto

industry standard.

The purpose of the ATA standard is to define the de facto implementations.

Software in the Operating System dispatches I/O (Input/Output) requests via

the AT Bus to peripherals which respond to direct commands.

3.1Structure

This standard relies upon specifications of the mechanical and electrical

characteristics of the AT Bus and a subset of the AT Bus specifically

developed for the direct attachment of peripherals.

Also defined are the methods by which commands are directed to peripherals,

the contents of registers and the method of data transfers.

4.Definitions and Conventions

4.1 Definitions

For the purpose of this standard the following definitions apply:

4.1.1 ATA (AT Attachment):ATA defines a compatible register set and a 40-pin

connector and its associated signals.

4.1.2 CHS (Cylinder-Head-Sector): This term defines the addressing mode of the

drive as being by physical address.

4.1.3 Data block: This term describes a data transfer, and is typically a

single sector, except when declared otherwise by use of the Set Multiple

command.

4.1.4 DMA (Direct Memory Access): A means of data transfer between

peripheral and host memory without processor intervention.

4.1.5 LBA (Logical Block Address): This term defines the addressing mode of

the drive as being by the linear mapping of sectors from 1 to n.

4.1.6 Optional:This term describes features which are not required by the

standard. However, if any feature defined by the standard is implemented, it

shall be done in the same way as defined by the standard. Describing a feature

as optional in the text is done to assist the reader. If there is a conflict

between text and tables on a feature described as optional, the table shall be

accepted as being correct.

4.1.7 PIO (Programmed Input/Output): A means of data transfer that requires

the use of the host processor.

4.1.8 Reserved:Where this term is used for bits, bytes and fields; the bits,

bytes and fields are set aside for future standardization, and shall be zero.

4.1.9 VU (Vendor Unique):This term is used to describe bits, bytes,

fields, code values and features which are not described in this standard,

and may be used in a way that varies between vendors.

4.2Conventions

Certain terms used herein are the proper names of signals. These are printed

in uppercase to avoid possible confusion with other uses of the same words;

e.g., ATTENTION. Any lowercase uses of these words have the normal American-

English meaning.

A number of conditions, commands, sequence parameters, events, English text,

states or similar terms are printed with the first letter of each word in

uppercase and the rest lowercase; e.g., In, Out, Request Status. Any lowercase

uses of these words have the normal American-English meaning.

The American convention of numbering is used i.e., the thousands and higher

multiples are separated by a comma and a period is used as the decimal point.

This is equivalent to the ISO convention of a space and comma.

American:0.6ISO:0,6

1,0001 000

1,323,462.91 323 462,9

5. Interface Cabling Requirements

5.1Configuration

This standard provides the capability of operating on the AT Bus in a daisy

chained configuration with a second drive that operates in accordance with

these standards. One drive (selected as Drive 0) has been referred to as the

master in industry terms and the second (selected as Drive 1) has been

referred to as the slave (see Figure 5-3).

The designation as Drive 0 or Drive 1 may be made in a number of ways:

- a switch on the drive

- a jumper plug on the drive

- use of the Cable Select (CSEL) pin

Data is transferred in parallel (8 or 16 bits) either to or from host memory

to the drive's buffer under the direction of commands previously transferred

from the host. The drive performs all of the operations necessary to properly

write data to, or read data from, the disk media. Data read from the media is

stored in the drive's buffer pending transfer to the host memory and data is

transferred from the host memory to the drive's buffer to be written to the

media.

+-----------------------------------------------------+

||

|HOST|

||

+---------------^-------------------------------------+

|ATA Interface

| _____________________

|/|

+------v--++------v--+

| DRIVE 0 || DRIVE 1 |

+---------++---------+

FIGURE 5-1:ATA INTERFACE TO EMBEDDED BUS PERIPHERALS

+-----------------------------------------------------+

||

|HOST|

||

+------+====== AT Bus ======+-------------------------+

||

|ADAPTER|

||

+--------^-----------+

|ATA Interface

| _____________________

|/|

+------v--++------v--+

| DRIVE 0 || DRIVE 1 |

+---------++---------+

FIGURE 5-2:HOST BUS ADAPTER AND PERIPHERAL DEVICES

+-----------------------------------------------------+

||

|HOST|

||

+---------------^-------------------------------------+

|ATA Interface

+------v-----+

||

| CONTROLLER |

||

+-^----^---^-+

|||__________________Device Interface

| ___|_________________|e.g. ESDI, SCSI

|/|||

+-v----v--++-v----v--+

|DRIVE||DRIVE|

+---------++---------+

FIGURE 5-3:ATA INTERFACE TO CONTROLLER AND PERIPHERAL DEVICES

5.2Addressing Considerations

In traditional controller operation, only the selected controller receives

commands from the host following selection. In this standard, the register

contents go to both drives (and their embedded controllers). The host

discriminates between the two by using the DRV bit in the Drive/Head Register.

5.3DC Cable and Connector

The drive receives DC power through a 4-pin or a low-power application 3-pin

connector.

A drive designed for 3.3V applications may be plugged into a receptacle

designed to accept a drive designed for 5V applications, with 12V lines for

additional power. It is not required that the drive operate, but it is

recommended that precautions be taken to prevent damage to the drive.

A drive designed for 5V applications may be plugged into a receptacle designed

to accept a drive designed for 3.3V applications, with 5V lines for additional

power. It is not anticipated that damage could occur to the drive, but it is

likely to fail in an undetermined manner.

5.3.14-Pin Power

The pin assignments are shown in Table 5-1. Recommended part numbers for the

mating connector to 18AWG cable are shown below, but equivalent parts may be

used.

Connector (4 Pin)AMP 1-480424-0 or equivalent.

Contacts (Loose Piece)AMP 60619-4 or equivalent.

Contacts (Strip)AMP 61117-4 or equivalent.

TABLE 5-1:DC INTERFACE

+------------------------+------------+

| POWER LINE DESIGNATION | PIN NUMBER |

+------------------------+------------+

|+12V|1-01|

|+12V RETURN|1-02|

|+5V RETURN|1-03|

|+5V|1-04|

+------------------------+------------+

5.3.23-Pin Power

The pin assignments are shown in Table 5-2. Recommended part numbers for the

mating connector to 18AWG cable are shown below, but equivalent parts may be

used.

Connector (3 Pin)Molex 5484 39-27-0032 or equivalent.

TABLE 5-2:DC INTERFACE

+------------------------+------------+

| POWER LINE DESIGNATION | PIN NUMBER |

+------------+-----------+------------+

|+5V|+3.3V|1-01|

|+12V|+5V|1-02|

|Ground|Ground|1-03|

+------------+-----------+------------+

5.3.3Device Grounding

System ground may be connected to a "quick-connect" terminal equivalent to:

Drive Connector TerminalAMP 61664-1 or equivalent.

Cable Connector TerminalAMP 62137-2 or equivalent.

Provision for tying the DC Logic ground and the chassis ground together or for

separating these two ground planes is vendor specific.

5.4I/O Connector

The I/O connector is a 40-pin connector as shown in Figure 5-4, with pin

assignments as shown in Table 6-1.

The connector should be keyed to prevent the possibility of installing it

upside down. A key is provided by the removal of Pin 20. The corresponding pin

on the cable connector should be plugged.

The pin locations are governed by the cable plug, not the receptacle. The way

in which the receptacle is mounted on the Printed Circuit Board affects the

pin positions, and pin 1 should remain in the same relative position. This

means the pin numbers of the receptacle may not reflect the conductor number

of the plug. The header receptacle is not polarized, and all the signals are

relative to Pin 20, which is keyed.

By using the plug positions as primary, a straight cable can connect drives.

As shown in Figure 5-4, conductor 1 on pin 1 of the plug has to be in the

same relative position no matter what the receptacle numbering looks like.

If receptacle numbering was followed, the cable would have to twist 180

degrees between a drive with top-mounted receptacles, and a drive with

bottom-mounted receptacles.

+-----------------------+

|1|

|40202|

==+==== Circuit Board ====+====+==== Circuit Board ====+==

|1|

|40202|

+-----------------------+

FIGURE 5-4:40-PIN CONNECTOR MOUNTING

Recommended part numbers for the mating connector are shown below, but

equivalent parts may be used.

Connector (40 Pin)3M 3417-7000 or equivalent.

Strain relief3M 3448-2040 or equivalent.

Flat Cable (Stranded 28 AWG)3M 3365-40 or equivalent.

Flat Cable (Stranded 28 AWG)3M 3517-40 (Shielded) or equivalent.

5.5I/O Cable

The cable specifications affect system integrity and the maximum length that

can be supported in any application.

TABLE 5-3:CABLE PARAMETERS

+--------------------------------------------+------+--------+

| Cable length of 0.46m (18 inches) *|Min |Max|

+--------------------------------------------+------+--------+

| Driver IoL Sink Current for 5V operation| 12mA ||

| Driver IoL Sink Current for 3.3V operation |8mA ||

| Driver IoH Source Current|| -400uA |

| Cable Capacitive Loading||200pF |

+--------------------------------------------+------+--------+

* This distance may be exceeded in circumstances where the

characteristics of both ends of the cable can be controlled.

作者：computer00  2005-10-12 12:19:00

6.Physical Interface

6.1Signal Conventions

Signal names are shown in all upper case letters. Signals can be asserted

(active, true) in either a high (more positive voltage) or low (less positive

voltage) state. A dash character (-) at the beginning or end of a signal name

indicates it is asserted at the low level (active low). No dash or a plus

character (+) at the beginning or end of a signal name indicates it is

asserted high (active high). An asserted signal may be driven high or low by

an active circuit, or it may be allowed to be pulled to the correct state by

the bias circuitry.

Control signals that are asserted for one function when high and asserted for

another function when low are named with the asserted high function name

followed by a slash character (/), and the asserted low function name followed

with a dash (-) e.g. BITENA/BITCLR- enables a bit when high and clears a bit

when low. All signals are TTL compatible unless otherwise noted. Negated means

that the signal is driven by an active circuit to the state opposite to the

asserted state (inactive, or false) or may be simply released (in which case

the bias circuitry pulls it inactive, or false), at the option of the

implementor.

Control signals that may be used for two mutually exclusive functions are

identified with their two names separated by a colon e.g. SPSYNC:CSEL can be

used for either the Spindle Sync or the Cable Select functions.

6.2Signal Summary

The physical interface consists of single ended TTL compatible receivers and

drivers communicating through a 40-conductor flat ribbon nonshielded cable

using an asynchronous interface protocol. The pin numbers and signal names

are shown in Table 6-1. Reserved signals shall be left unconnected.

TABLE 6-1:INTERFACE SIGNALS

+----------------------------------++-----------+

|HOSTI/O|| DRIVE I/O |

|CONNECTOR|| CONNECTOR |

||||

| HOST RESET1 | -----RESET--------->| 1|

|2 | -----Ground-------- | 2|

| HOST DATA BUS BIT 73 |<-----DD7----------->| 3|

| HOST DATA BUS BIT 84 |<-----DD8----------->| 4|

| HOST DATA BUS BIT 65 |<-----DD6----------->| 5|

| HOST DATA BUS BIT 96 |<-----DD9----------->| 6|

| HOST DATA BUS BIT 57 |<-----DD5----------->| 7|

| HOST DATA BUS BIT 108 |<-----DD10---------->| 8|

| HOST DATA BUS BIT 49 |<-----DD4----------->| 9|

| HOST DATA BUS BIT 1110 |<-----DD11---------->| 10|

| HOST DATA BUS BIT 311 |<-----DD3----------->| 11|

| HOST DATA BUS BIT 1212 |<-----DD12---------->| 12|

| HOST DATA BUS BIT 213 |<-----DD2----------->| 13|

| HOST DATA BUS BIT 1314 |<-----DD13---------->| 14|

| HOST DATA BUS BIT 115 |<-----DD1----------->| 15|

| HOST DATA BUS BIT 1416 |<-----DD14---------->| 16|

| HOST DATA BUS BIT 017 |<-----DD0----------->| 17|

| HOST DATA BUS BIT 1518 |<-----DD15---------->| 18|

|19 | -----Ground-------- | 19|

|20 | -----(keypin)------ | 20|

| DMA REQUEST21 |<-----DMARQ--------- | 21|

|22 | -----Ground-------- | 22|

| HOST I/O WRITE23 | -----DIOW---------->| 23|

|24 | -----Ground-------- | 24|

| HOST I/O READ25 | -----DIOR---------->| 25|

|26 | -----Ground-------- | 26|

| I/O CHANNEL READY27 |<-----IORDY--------- | 27|

| SPINDLE SYNC or CABLE SELECT28 |*---- SPSYNC:CSEL-----*| 28|

| DMA ACKNOWLEDGE29 | -----DMACK--------->| 29|

|30 | -----Ground-------- | 30|

| HOST INTERRUPT REQUEST31 |<-----INTRQ--------- | 31|

| HOST 16 BIT I/O32 |<-----IOCS16-------- | 32|

| HOST ADDRESS BUS BIT 133 | -----DA1----------->| 33|

| PASSED DIAGNOSTICS34 |*-----PDIAG---------*| 34|

| HOST ADDRESS BUS BIT 035 | -----DAO----------->| 35|

| HOST ADDRESS BUS BIT 236 | -----DA2----------->| 36|

| HOST CHIP SELECT 037 | -----CS1FX--------->| 37|

| HOST CHIP SELECT 138 | -----CS3FX--------->| 38|

| DRIVE ACTIVE/DRIVE 1 PRESENT39 |<-----DASP----------*| 39|

|40 | -----Ground-------- | 40|

+----------------------------------++-----------+

* Drive Intercommunication Signals

+---HOST---++-Drive 0-++-Drive 1-+

|28 | ----->| 2828 |<-- SPSYNC:CSEL-->| 28|

|34 | ----- | 3434 |<----- PDIAG----- | 34|

|39 |<----- | 3939 |<----- DASP------ | 39|

+----------++---------++---------+

6.3Signal Descriptions

The interface signals and pins are described in more detail than shown in

Table 6-1. The signals are listed according to function, rather than in

numerical connector pin order. Table 6-2 lists signal name mnemonic, connector

pin number, whether input to (I) or output from (O) the drive, and full signal

name.

TABLE 6-2:INTERFACE SIGNALS DESCRIPTION

+--------+----+-----+

| Signal | Pin| I/O |

+--------+----+-----+-----------------------------------------------------+

| CS1FX- | 37 |I| Drive chip Select 0|

| CS3FX- | 38 |I| Drive chip Select 1|

| DA0| 35 |I| Drive Address Bus - Bit 0|

| DA1| 33 |I|- Bit 1|

| DA2| 36 |I|- Bit 2|

| DASP-| 39 | I/O | Drive Active/Drive 1 Present|

| DD0| 17 | I/O | Drive Data Bus - Bit 0|

| DD1| 15 | I/O |- Bit 1|

| DD2| 13 | I/O |- Bit 2|

| DD3| 11 | I/O |- Bit 3|

| DD4|9 | I/O |- Bit 4|

| DD5|7 | I/O |- Bit 5|

| DD6|5 | I/O |- Bit 6|

| DD7|3 | I/O |- Bit 7|

| DD8|4 | I/O |- Bit 8|

| DD9|6 | I/O |- Bit 9|

| DD10|8 | I/O |- Bit 10|

| DD11| 10 | I/O |- Bit 11|

| DD12| 12 | I/O |- Bit 12|

| DD13| 14 | I/O |- Bit 13|

| DD14| 16 | I/O |- Bit 14|

| DD15| 18 | I/O |- Bit 15|

| DIOR-| 25 |I| Drive I/O Read|

| DIOW-| 23 |I| Drive I/O Write|

| DMACK- | 29 |I| DMA Acknowledge|

| DMARQ| 21 |O| DMA Request|

| INTRQ| 31 |O| Drive Interrupt|

| IOCS16-| 32 |O| Drive 16-bit I/O|

| IORDY| 27 |O| I/O Channel Ready|

| PDIAG- | 34 | I/O | Passed Diagnostics|

| RESET- |1 |I| Drive Reset|

| SPSYNC:| 28 |-| Spindle Sync|

| CSEL| 28 |-| Cable Select|

| keypin | 20 |-| Pin used for keying the interface connector.|

+--------+----+-----+-----------------------------------------------------+

6.3.1 CS1FX- (Drive chip Select 0)

This is the chip select signal decoded from the host address bus used to

select the Command Block Registers.

6.3.2 CS3FX- (Drive chip Select 1)

This is the chip select signal decoded from the host address bus used to

select the Control Block Registers.

6.3.3 DA0-2 (Drive Address Bus)

This is the 3-bit binary coded address asserted by the host to access a

register or data port in the drive.

6.3.4 DASP- (Drive Active/Drive 1 Present)

This is a time-multiplexed signal which indicates that a drive is active, or

that Drive 1 is present. This signal shall be an open collector output and

each drive shall have a 10K ohm pull-up resistor.

During power on initialization or after RESET- is negated, DASP- shall be

asserted by Drive 1 within 400 msec to indicate that Drive 1 is present.

Drive 0 shall allow up to 450 msec for Drive 1 to assert DASP-. If Drive 1 is

not present, Drive 0 may assert DASP- to drive an activity LED.

DASP- shall be negated following acceptance of the first valid command by

Drive 1 or after 31 seconds, whichever comes first.

Any time after negation of DASP-, either drive may assert DASP- to indicate

that a drive is active.

NOTE: Prior to the development of this standard, products were introduced

which did not time multiplex DASP-. Some used two jumpers to indicate

to Drive 0 whether Drive 1 was present. If such a drive is jumpered to

indicate Drive 1 is present it should work successfully with a Drive 1

which complies with this standard. If installed as Drive 1, such a

drive may not work successfully because it may not assert DASP- for a

long enough period to be recognized. However, it would assert DASP-

to indicate that the drive is active.

6.3.5 DD0-DD15 (Drive Data Bus)

This is an 8- or 16-bit bidirectional data bus between the host and the drive.

The lower 8 bits are used for 8-bit transfers e.g. registers, ECC bytes and,

if the drive supports the Features Register capability to enable 8-bit-only

data transfers (see 9.21).

6.3.6 DIOR- (Drive I/O Read)

This is the Read strobe signal. The falling edge of DIOR- enables data from a

register or the data port of the drive onto the host data bus, DD0-DD7 or DD0-

DD15. The rising edge of DIOR- latches data at the host.

6.3.7 DIOW- (Drive I/O Write)

This is the Write strobe signal. The rising edge of DIOW- clocks data from the

host data bus, DD0-DD7 or DD0-DD15, into a register or the data port of the

drive.

6.3.8 DMACK- (DMA Acknowledge) (Optional)

This signal shall be used by the host in response to DMARQ to either

acknowledge that data has been accepted, or that data is available.

6.3.9 DMARQ (DMA Request) (Optional)

This signal, used for DMA data transfers between host and drive, shall be

asserted by the drive when it is ready to transfer data to or from the host.

The direction of data transfer is controlled by DIOR- and DIOW-. This signal

is used in a handshake manner with DMACK- i.e. the drive shall wait until the

host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is

more data to transfer.

When a DMA operation is enabled, IOCS16-, CS1FX- and CS3FX- shall not be

asserted and transfers shall be 16-bits wide.

NOTE: ATA products with DMA capability require a pull-down resistor on this

signal to prevent spurious data transfers. This resistor may affect

driver requirements for drives sharing this signal in systems with

unbuffered ATA signals.

6.3.10 INTRQ (Drive Interrupt)

This signal is used to interrupt the host system. INTRQ is asserted only when

the drive has a pending interrupt, the drive is selected, and the host has

cleared nIEN in the Device Control Register. If nIEN=1, or the drive is not

selected, this output is in a high impedance state, regardless of the presence

or absence of a pending interrupt.

INTRQ shall be negated by:

- assertion of RESET- or

- the setting of SRST of the Device Control Register, or

- the host writing the Command Register or

- the host reading the Status Register

NOTE: Some drives may negate INTRQ on a PIO data transfer completion, except

on a single sector read or on the last sector of a multi-sector read.

On PIO transfers, INTRQ is asserted at the beginning of each data block to be

transferred. A data block is typically a single sector, except when

declared otherwise by use of the Set Multiple command. An exception occurs on

Format Track, Write Sector(s), Write Buffer and Write Long commands - INTRQ

shall not be asserted at the beginning of the first data block to be

transferred.

On DMA transfers, INTRQ is asserted only once, after the command has

completed.

6.3.11 IOCS16- (Drive 16-bit I/O)

Except for DMA transfers, IOCS16- indicates to the host system that the 16-bit

data port has been addressed and that the drive is prepared to send or receive

a 16-bit data word. This shall be an open collector output.

- When transferring in PIO mode, If IOCS16- is not asserted, transfers shall

be 8-bit using DD0-7.

- When transferring in PIO mode, if IOCS16- is asserted, transfers shall be

16-bit using DD0-15.

for 16-bit data transfers.

- When transferring in DMA mode, the host shall use a 16-bit DMA channel and

IOCS16- shall not be asserted.

6.3.12 IORDY (I/O Channel Ready) (Optional)

This signal is negated to extend the host transfer cycle of any host register

access (Read or Write) when the drive is not ready to respond to a data

transfer request. When IORDY is not negated, IORDY shall be in a high

impedance state.

6.3.13 PDIAG- (Passed Diagnostics)

This signal shall be asserted by Drive 1 to indicate to Drive 0 that it has

completed diagnostics. A 10K ohm pull-up resistor shall be used on this signal

by each drive.

Following a power on reset, software reset or RESET-, Drive 1 shall negate

PDIAG- within 1 msec (to indicate to Drive 0 that it is busy). Drive 1 shall

then assert PDIAG- within 30 seconds to indicate that it is no longer busy,

and is able to provide status. After the assertion of PDIAG-, Drive 1 may be

unable to accept commands until it has finished its reset procedure and is

Ready (DRDY=1).

Following the receipt of a valid Execute Drive Diagnostics command, Drive

1 shall negate PDIAG- within 1 msec to indicate to Drive 0 that it is busy

and has not yet passed its drive diagnostics. If Drive 1 is present then

Drive 0 shall wait for up to 5 seconds from the receipt of a valid Execute

Drive Diagnostics command for Drive 1 to assert PDIAG-. Drive 1 should

clear BSY before asserting PDIAG-, as PDIAG- is used to indicate that

Drive 1 has passed its diagnostics and is ready to post status.

If DASP- was not asserted by Drive 1 during reset initialization, Drive 0

shall post its own status immediately after it completes diagnostics, and

clear the Drive 1 Status Register to 00h. Drive 0 may be unable to accept

commands until it has finished its reset procedure and is Ready (DRDY=1).

6.3.14 RESET- (Drive Reset)

This signal from the host system shall be asserted for at least 25 usec after

voltage levels have stabilized during power on and negated thereafter unless

some event requires that the drive(s) be reset following power on.

6.3.15SPSYNC:CSEL (Spindle Synchronization/Cable Select) (Optional)

This signal shall have a 10K ohm pull-up resistor.

This is a dual purpose signal and either or both functions may be implemented.

If both functions are implemented then they cannot be active concurrently: the

choice as to which is active is made by a vendor-defined switch.

All drives connected to the same cable should have the same function active at

the same time. If SPSYNC and CSEL are mixed on the same cable, then drive

behaviour is undefined.

Prior to the introduction of this standard, this signal was defined as DALE

(Drive Address Latch Enable), and used for an address valid indication from

the host system. If used, the host address and chip selects, DAO through DA2,

CS1FX-, and CS3FX- were valid at the negation of this signal and remained

valid while DALE was negated, therefore, the drive did not need to latch these

signals with DALE.

6.3.15.1SPSYNC (Spindle Synchronization) (Optional)

This signal may be either input or output to the drive depending on a vendor-

defined switch. If a drive is set to Master the signal is output, and if a

drive is set to slave the signal is input.

There is no requirement that each drive implementation be plug-compatible to

the extent that a multiple vendor drive subsystem be operable. Mix and match

of different manufacturers drives is unlikely because rpm, sync fields, sync

bytes etc need to be virtually identical. However, if drives are designed to

match the following recommendation, controllers can operate drives with a

single implementation.

There can only be one master drive at a time in a configuration. The host or

the drive designated as master can generate SPSYNC at least once per rotation,

but may be at a higher frequency.

SPSYNC received by a drive is used as the synchronization signal to lock the

spindles in step. The time to achieve synchronization varies, and is indicated

by the drive setting DRDY i.e. if the drive does not achieve synchronization

following power on or a reset, it shall not set DRDY.

A master drive or the host generates SPSYNC and transmits it.

A slave drive does not generate SPSYNC and is responsible to synchronize its

index to SPSYNC.

If a drive does not support synchronization, it shall ignore SPSYNC.

In the event that a drive previously synchronized loses synchronization, but

is otherwise operational, it does not clear DRDY.

6.3.15.2CSEL (Cable Select) (Optional)

The drive is configured as either Drive 0 or Drive 1 depending upon the value

of CSEL:

- If CSEL is grounded then the drive address is 0

- If CSEL is open then the drive address is 1

Special cabling can be used by the system manufacturer to selectively ground

CSEL e.g. CSEL of Drive 0 is connected to the CSEL conductor in the cable, and

is grounded, thus allowing the drive to recognize itself as Drive 0. CSEL of

Drive 1 is not connected to CSEL because the conductor is removed, thus the

drive can recognize itself as Drive 1.

______ CSEL Conductor _________________________

||Open

|Ground||

+------++---------++---------+

| Host || Drive 0 || Drive 1 |

+------++---------++---------+

______ CSEL Conductor _________________________

|Open|

|Ground||

+------++---------++---------+

| Host || Drive 1 || Drive 0 |

+------++---------++---------+

FIGURE 6-1:Cable Select

7.Logical Interface

7.1General

7.1.1Bit Conventions

Bit names are shown in all upper case letters except where a lower case n

precedes a bit name. This indicates that when nBIT=0 (bit is zero) the action

is true and when nBIT=1 (bit is one) the action is false. If there is no

preceding n, then when BIT=1 it is true, and when BIT=0 it is false.

A bit can be set to one or cleared to zero and polarity influences whether it

is to be interpreted as true or false:

TrueBIT=1nBIT=0

FalseBIT=0nBIT=1

7.1.2Environment

The drives using this interface shall be programmed by the host computer to

perform commands and return status to the host at command completion. When two

drives are daisy chained on the interface, commands are written in parallel to

both drives, and for all except the Execute Diagnostics command, only the

selected drive executes the command. On an Execute Diagnostics command

addressed to Drive 0, both drives shall execute the command, and Drive 1 shall

post its status to Drive 0 via PDIAG-.

Drives are selected by the DRV bit in the Drive/Head Register (see 7.2.8), and

by a jumper or switch on the drive designating it as either a Drive 0 or as

Drive 1. When DRV=0, Drive 0 is selected. When DRV=1, Drive 1 is selected.

When drives are daisy chained, one shall be set as Drive 0 and the other as

Drive 1. When a single drive is attached to the interface it shall be set as

Drive 0.

Prior to the adoption of this standard, some drives may have provided jumpers

to indicate Drive 0 with no Drive 1 present, or Drive 0 with Drive 1 present.

Throughout this document, drive selection always refers to the state of the

DRV bit, the position of the Drive 0/Drive 1 jumper or switch, or use of the

CSEL pin.

A drive can operate in either of two addressing modes, CHS or LBA, on a

command by command basis. A drive which can support LBA mode indicates this in

the Identify Drive Information. If the host selects LBA mode in the Drive/Head

register, Sector Number, Cylinder Low, Cylinder High and HS3-HS0 of the

Drive/Head Register contains the zero based-LBA.

In LBA mode, the sectors on the drive are assumed to be linearly mapped with

an Inital definition of:

LBA 0 = Cylinder 0/Head 0/Sector 1.

Irrespective of translate mode geometry set by the host, the LBA address of a

given sector does not change:

LBA = [ (Cylinder * No of Heads + Heads) * Sectors/Track ] + (Sector-1)

7.2I/O Register Descriptions

Communication to or from the drive is through an I/O Register that routes the

input or output data to or from registers (selected) by a code on signals from

the host (CS1FX-, CS3FX-, DA2, DA1, DA0, DIOR- and DIOW-).

The Command Block Registers are used for sending commands to the drive or

posting status from the drive.

The Control Block Registers are used for drive control and to post alternate

status.

Table 7-1 lists these registers and the addresses that select them.

Logic conventions are:A = signal asserted

N = signal negated

x = does not matter which it is

TABLE 7-1:I/O PORT FUNCTIONS/SELECTION ADDRESSES

+-------------------------------+-----------------------------------------+

|Addresses|Functions|

|CS1FX-|CS3FX-| DA2 | DA1 | DA0 |READ (DIOR-)|WRITE (DIOW-)|

+------+------+-----+-----+-----+---------------------+-------------------+

|Control Block Registers|

+------+------+-----+-----+-----+---------------------+-------------------+

|N|N|x|x|x| Data Bus High Imped | Not used|

|N|A|0|x|X| Data Bus High Imped | Not used|

|N|A|1|0|x| Data Bus High Imped | Not used|

|N|A|1|1|0| Alternate Status| Device Control|

|N|A|1|1|1| Drive Address| Not used|

+------+------+-----+-----+-----+---------------------+-------------------+

|Command Block Registers|

+------+------+-----+-----+-----+---------------------+-------------------+

|A|N|0|0|0| Data| Data|

|A|N|0|0|1| Error Register| Features|

|A|N|0|1|0| Sector Count| Sector Count|

|A|N|0|1|1| Sector Number| Sector Number|

|A|N|0|1|1| * LBA Bits0- 7| * LBA Bits0- 7|

|A|N|1|0|0| Cylinder Low| Cylinder Low|

|A|N|1|0|0| * LBA Bits8-15| * LBA Bits8-15|

|A|N|1|0|1| Cylinder High| Cylinder High|

|A|N|1|0|1| * LBA Bits 16-23| * LBA Bits 16-23|

|A|N|1|1|0| Drive/Head| Drive/Head|

|A|N|1|1|0| * LBA Bits 24-27| * LBA Bits 24-27|

|A|N|1|1|1| Status| Command|

|A|A|x|x|x| Invalid Address| Invalid Address|

+------+------+-----+-----+-----+---------------------+-------------------+

* Mapping of registers in LBA Mode

7.2.1Alternate Status Register

This register contains the same information as the Status Register in the

command block. The only difference being that reading this register does not

imply interrupt acknowledge or clear a pending interrupt.

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

|BSY| DRDY|DWF|DSC|DRQ| CORR|IDX|ERR|

+-------+-------+-------+-------+-------+-------+-------+-------+

See 7.2.13 for definitions of the bits in this register.

7.2.2Command Register

This register contains the command code being sent to the drive. Command

execution begins immediately after this register is written. The executable

commands, the command codes, and the necessary parameters for each command are

listed in Table 9-1.

7.2.3Cylinder High Register

This register contains the high order bits of the starting cylinder address

for any disk access. At the end of the command, this register is updated to

reflect the current cylinder number. The most significant bits of the cylinder

address shall be loaded into the cylinder high Register.

In LBA Mode this register contains Bits 16-23. At the end of the command, this

register is updated to reflect the current LBA Bits 16-23.

NOTE: Prior to the introduction of this standard, only the lower 2 bits of

this register were valid, limiting cylinder address to 10 bits i.e.

1,024 cylinders.

7.2.4Cylinder Low Register

This register contains the low order 8 bits of the starting cylinder address

for any disk access. At the end of the command, this register is updated to

reflect the current cylinder number.

In LBA Mode this register contains Bits 8-15. At the end of the command, this

register is updated to reflect the current LBA Bits 8-15.

7.2.5Data Register

This 16-bit register is used to transfer data blocks between the device data

buffer and the host. It is also the register through which sector information

is transferred on a Format Track command. Data transfers may be either PIO or

DMA.

7.2.6Device Control Register

The bits in this register are as follows:

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

|x|x|x|x|1| SRST|nIEN |0|

+-------+-------+-------+-------+-------+-------+-------+-------+

- SRST is the host software reset bit. The drive is held reset when this bit

is set. If two disk drives are daisy chained on the interface, this bit

resets both simultaneously. Drive 1 is not required to execute the DASP-

handshake procedure.

- nIEN is the enable bit for the drive interrupt to the host. When nIEN=0,

and the drive is selected, INTRQ shall be enabled through a tri-state

buffer. When nIEN=1, or the drive is not selected, the INTRQ signal shall

be in a high impedance state.

7.2.7Drive Address Register

This register contains the inverted drive select and head select addresses of

the currently selected drive. The bits in this register are as follows:

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

|HiZ|nWTG |nHS3 |nHS2 |nHS1 |nHS0 |nDS1 |nDS0 |

+-------+-------+-------+-------+-------+-------+-------+-------+

- HiZ shall always be in a high impedance state.

- nWTG is the Write Gate bit. When writing to the disk drive is in progress,

nWTG=0.

- nHS3 through nHS0 are the one's complement of the binary coded address of

the currently selected head. For example, if nHS3 through nHS0 are 1100b,

respectively, head 3 is selected. nHS3 is the most significant bit.

- nDS1 is the drive select bit for drive 1. When drive 1 is selected and

active, nDS1=0.

- nDS0 is the drive select bit for drive 0. When drive 0 is selected and

active, nDS0=0.

NOTE: Care should be used when interpreting these bits, as they do not

always represent the expected status of drive operations at the

instant the status was put into this register. This is because of the

use of cacheing, translate mode and the Drive 0/Drive 1 concept with

each drive having its own embedded controller.

7.2.8Drive/Head Register

This register contains the drive and head numbers. The contents of this

register define the number of heads minus 1, when executing an Initialize

Drive Parameters command.

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

|1|L|1|DRV|HS3|HS2|HS1|HS0|

+-------+-------+-------+-------+-------+-------+-------+-------+

- L is the binary encoded address mode select. When L=0, addressing is by CHS

mode. When L=1, addressing is by LBA mode.

- DRV is the binary encoded drive select number. When DRV=0, Drive 0 is

selected. When DRV=1, Drive 1 is selected.

- If L=0, HS3 through HS0 contain the binary coded address of the head to be

selected e.g. if HS3 through HS0 are 0011b, respectively, head 3 will be

selected. HS3 is the most significant bit. At command completion, these

bits are updated to reflect the currently selected head.

If L=1, HS3 through HS0 contain bits 24-27 of the LBA. At command

completion, these bits are updated to reflect the current LBA bits 24-27.

7.2.9Error Register

This register contains status from the last command executed by the drive or a

Diagnostic Code.

At the completion of any command except Execute Drive Diagnostic, the contents

of this register are valid when ERR=1 in the Status Register.

Following a power on, a reset, or completion of an Execute Drive Diagnostic

command, this register contains a Diagnostic Code (see Table 9-2).

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

| BBK|UNC|MC|IDNF |MCR| ABRT| TK0NF |AMNF |

+-------+-------+-------+-------+-------+-------+-------+-------+

- BBK (Bad Block Detected) indicates a bad block mark was detected in the

requested sector's ID field.

- UNC (Uncorrectable Data Error) indicates an uncorrectable data error has

been encountered.

- MC (Media Changed) indicates that the removable media has been changed i.e.

there has been a change in the ability to access the media.

- IDNF (ID Not Found) indicates the requested sector's ID field could not be

found.

- ABRT (Aborted Command) indicates the requested command has been aborted due

to a drive status error (Not Ready, Write Fault, etc.) or because the

command code is invalid.

- MCR (Media Change Requested) indicates that the release latch on a

removable media drive has been pressed. This means that the user wishes to

remove the media and requires an action of some kind e.g. have software

issue a Media Eject or Door Unlock command.

- TK0NF (Track 0 Not Found) indicates track 0 has not been found during a

Recalibrate command.

- AMNF (Address Mark Not Found) indicates the data address mark has not been

found after finding the correct ID field.

7.2.10Features Register

This register is command specific and may be used to enable and disable

features of the interface e.g. by the Set Features Command to enable and

disable cacheing.

This register may be ignored by some drives.

Some hosts, based on definitions prior to the completion of this standard, set

values in this register to designate a recommended Write Precompensation

Cylinder value.

7.2.11Sector Count Register

This register contains the number of sectors of data requested to be

transferred on a read or write operation between the host and the drive. If

the value in this register is zero, a count of 256 sectors is specified.

If this register is zero at command completion, the command was successful. If

not successfully completed, the register contains the number of sectors which

need to be transferred in order to complete the request.

The contents of this register may be defined otherwise on some commands e.g.

Initialize Drive Parameters, Format Track or Write Same commands.

作者：computer00  2005-10-12 12:32:00

7.2.12Sector Number Register

This register contains the starting sector number for any disk data access for

the subsequent command. The sector number may be from 1 to the maximum number

of sectors per track.

In LBA Mode this register contains Bits 0-7. At the end of the command, this

register is updated to reflect the current LBA Bits 0-7.

See the command descriptions for contents of the register at command

completion (whether successful or unsuccessful).

7.2.13Status Register

This register contains the drive status. The contents of this register are

updated at the completion of each command. When BSY is cleared, the other bits

in this register shall be valid within 400 nsec. If BSY=1, no other bits in

this register are valid. If the host reads this register when an interrupt is

pending, it is considered to be the interrupt acknowledge. Any pending

interrupt is cleared whenever this register is read.

NOTE: If Drive 1 is not detected as being present, Drive 0 clears the Drive

1 Status Register to 00h (indicating that the drive is Not Ready).

76543210

+-------+-------+-------+-------+-------+-------+-------+-------+

|BSY| DRDY|DWF|DSC|DRQ| CORR|IDX|ERR|

+-------+-------+-------+-------+-------+-------+-------+-------+

NOTE: Prior to the definition of this standard, DRDY and DSC were unlatched

real time signals.

- BSY (Busy) is set whenever the drive has access to the Command Block

Registers. The host should not access the Command Block Register when

BSY=1. When BSY=1, a read of any Command Block Register shall return the

contents of the Status Register. This bit is set by the drive (which may be

able to respond at times when the media cannot be accessed) under the

following circumstances:

a) within 400 nsec after the negation of RESET- or after SRST has been set

in the Device Control Register. Following acceptance of a reset it is

recommended that BSY be set for no longer than 30 seconds by Drive 1 and

no longer than 31 seconds by Drive 0.

b) within 400 nsec of a host write of the Command Register with a Read,

Read Long, Read Buffer, Seek, Recalibrate, Initialize Drive Parameters,

Read Verify, Identify Drive, or Execute Drive Diagnostic command.

c) within 5 usecs following transfer of 512 bytes of data during execution

of a Write, Format Track, or Write Buffer command, or 512 bytes of data

and the appropriate number of ECC bytes during the execution of a Write

Long command.

- DRDY (Drive Ready) indicates that the drive is capable of responding to a

command. When there is an error, this bit is not changed until the Status

Register is read by the host, at which time the bit again indicates the

current readiness of the drive. This bit shall be cleared at power on and

remain cleared until the drive is ready to accept a command.

- DWF (Drive Write Fault) indicates the current write fault status. When an

error occurs, this bit shall not be changed until the Status Register is

read by the host, at which time the bit again indicates the current write

fault status.

- DSC (Drive Seek Complete) indicates that the drive heads are settled over a

track. When an error occurs, this bit shall not be changed until the Status

Register is read by the host, at which time the bit again indicates the

current Seek Complete status.

- DRQ (Data Request) indicates that the drive is ready to transfer a word or

byte of data between the host and the drive.

- CORR (Corrected Data) indicates that a correctable data error was

encountered and the data has been corrected. This condition does not

terminate a data transfer.

- IDX (Index) is set once per disk revolution.

- ERR (Error) indicates that an error occurred during execution of the

previous command. The bits in the Error Register have additional

information regarding the cause of the error.

8.Programming Requirements

8.1Reset Response

A reset is accepted within 400 nsec after the negation of RESET- or within 400

nsec after SRST has been set in the Device Control Register.

When the drive is reset by RESET-, Drive 1 shall indicate it is present by

asserting DASP- within 400 msec, and DASP- shall remain asserted for 30

seconds or until Drive 1 accepts the first command. See also 6.3.4 and 6.3.13.

When the drive is reset by SRST, the drive shall set BSY=1.

See also 7.2.6.

When a reset is accepted, and with BSY set:

a) Both drives perform any necessary hardware initialization

b) Both drives clear any previously programmed drive parameters

c) Both drives may revert to the default condition

d) Both drives load the Command Block Registers with their default values

e) If a hardware reset, Drive 0 waits for DASP- to be asserted by Drive 1

f) If operational, Drive 1 asserts DASP-

g) Drive 0 waits for PDIAG- to be asserted if Drive 1 asserts DASP-

h) If operational, Drive 1 clears BSY

i) If operational, Drive 1 asserts PDIAG-

j) Drive 0 clears BSY

No interrupt is generated when initialization is complete.

The default values for the Command Block Registers if no self-tests are

performed or if no errors occurred are:

Error= 01hCylinder Low= 00h

Sector Count= 01hCylinder High = 00h

Sector Number = 01hDrive/Head= 00h

The Error Register shall contain a Diagnostic Code (see Table 9.2) if a self-

test is performed.

Following any reset, the host should issue an Initialize Drive Parameters

command to ensure the drive is initialized as desired.

There are three types of reset in ATA. The following is a suggested method of

classifying reset actions:

- Power On Reset: the drive executes a series of electrical circuitry

diagnostics, spins up the HDA, tests speed and other mechanical

parametrics, and sets default values.

- Hardware Reset: the drive executes a series of electrical circuitry

diagnostics, and resets to default values.

- Software Reset: the drive resets the interface circuitry according to the

Set Features requirement (See 9.21)

8.2Translate Mode

The cylinder, head and sector geometry of the drive as presented to the host

may differ from the actual physical geometry. Translate mode is an optional

and device specific means of mapping between the two.

8.3Power Conditions

Optional power commands permit the host to modify the behavior of the drive in

a manner which reduces the power required to operate.

TABLE 8-1:POWER CONDITIONS

+----------+----+----+----+------------------+-----+

|Mode|SRST| BSY|DRDY| Interface Active |Media|

+----------+----+----+----+------------------+-----+

| Sleep|* |x |x |*|0|

|||||||

| Standby|x |0 |1 |Yes|0|

|||||||

| Idle|x |0 |1 |Yes|1|

|||||||

| Active|x |x |x |Yes|1|

+----------+----+----+----+------------------+-----+

|1 = Active0 = Inactive* See 9.23|

+--------------------------------------------------+

The lowest power consumption when the drive is powered on occurs in Sleep

mode. When in Sleep mode, the drive requires a reset to be activated (see

9.23). The time to respond could be as long as 30 seconds or more.

In Standby mode the drive interface is capable of accepting commands, but as

the media is not immediately accessible, it could take the drive as long as 30

seconds or more to respond.

In Idle mode the drive is capable of responding immediately to media access

requests. A drive in Idle mode may take longer to complete the execution of a

command because it may have to activate some circuitry.

In Active mode the drive is capable of responding immediately to media access

requests, and commands complete execution in the shortest possible time.

Ready is not a power condition. A drive may post ready at the interface even

though the media may not be accessible.

See specific power-related commands.

8.4Error Posting

The errors that are valid for each command are defined in Table 8-1. It is not

a requirement that all valid conditions be implemented. See 7.2.9 and 7.2.13

for the definition of the Error Register and Status Register bits.

TABLE 8-2:REGISTER CONTENTS

+----------------------------+---------------------+

|Error Register|Status Register|

|BBK|UNC|IDNF|ABRT|TK0NF|AMNF|DRDY|DWF|DSC|CORR|ERR|

+------------------------+---+---+----+----+-----+----+----+---+---+----+---+

| Acknowledge Media Chge ||||V ||||||||

| Boot - Post-Boot||||V ||||||||

| Boot - Pre-Boot||||V ||||||||

| Check Power Mode||||V |||V | V | V || V |

| Door Lock|||V |V |||V |||||

| Door Unlock||||V ||||||||

| Execute Drive Diags|See 9.7||||| V |

| Format Track|||V |V |||V | V | V || V |

| Identify Drive||||V |||V | V | V || V |

| Idle||||V |||V | V | V || V |

| Idle Immediate||||V |||V | V | V || V |

| Initialize Drive Parms |||||||V | V | V |||

| NOP||||V ||||||| V |

| Read Buffer||||V |||V | V | V || V |

| Read DMA| V | V |V |V ||V |V | V | V |V | V |

| Read Long| V ||V |V ||V |V | V | V || V |

| Read Multiple| V | V |V |V ||V |V | V | V |V | V |

| Read Sector(s)| V | V |V |V ||V |V | V | V |V | V |

| Read Verify Sector(s)| V | V |V |V ||V |V | V | V |V | V |

| Recalibrate||||V |V||V | V | V || V |

| Seek|||V |V |||V | V | V || V |

| Set Features||||V |||V | V | V || V |

| Set Multiple Mode||||V |||V | V | V || V |

| Sleep||||V |||V | V | V || V |