IP1725-LF IP1725

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IP1725-LF   IP1725    有现货 可添加我们联系方式获取最优惠价格
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IP1725是成本有效和完全集成的单芯片。
它集成了一个25-port开关控制器,
一个3 x八进制PHY收发器和SSRAM。
每个PHY收发器符合802.3 u规范和HP-license汽车MDI / MDIX。

S25 Ports 10/100Mb Ethernet Layer 2 Smart Switch
- Built-in 24 PHYs
- One MII interface
Store & Forward, Share Memory Non_blocking Architecture
- Built-in 2.5Mb SRAM (1.75Mb for packet buffer)
- Max. length 1664B
Wire-speed Operation On Every Port
Head Of Line Blocking Prevention
Flow Control Support
- 802.3x compliant flow control in full duplex
- Collision/Carrier_snese based backpressure in half duplex
Internal 8K MAC Address Entities
- CRC/direct hashing algorithm
- Aging timer programmable (55s~251.6hr) < 4 %
- Wire speed address learning and resolution
- CPU accessible for security and static MAC
- Learning enable/disable
Sniffer Function Support (in/out/in+out)
IGMP Snooping Support
- Version 1 , 2
- Snooping by Switch ASIC or external CPU
Two Trunk Group Support
- Two trunk groups, each trunk has 4 ports (max)
- The ports belong to trunk group are configurable
- Load balance based on (Port ID, DA , SA, DA/SA)
- Link fault recovery
VLAN (32 VLAN groups)
- Port based
- Tagged based
- Tag remove/add/modify support
- Special TAG support
- Protected VLAN
- Q-in-Q (double tag) support
Class Of Service (CoS) Support
- Port based
- 802.1Q priority based tagged based
- IP TOS based (IPv4/IPv6)
- TCP/UDP port number based
- Destination MAC address based
- IP address based
- 4 levels per port
- WRR/FIFS/SP/SP+WRR
- ACL based
Broadcast Storm Control
- Broadcast rate control per port selectable
- With option to drop all ARP to CPU
- Also has ARP and ICMP storm control
Multi-cast/unknown DA frames can be counted
Port Security
- MAC based
- IP(DIP/SIP) based (IPv4 32 bit only
- TCP/UDP port based
- Port based
Bandwidth Control
- 32K bpsxN 256 levels
- 512K bpsxN 256 levels
- With flow control/Without flow control
- WAN port control support
Support SMI Interface Auto-polling
- Speed, Duplex, Flow control, Link
- CPU accessible (interrupt support)
- CPU R/W PHY register
Out Queue Aging Function
- From 100 ms to 6.3 sec selectable
Spanning Tree Protocol Port State Support
- Discard/Block/Learning/Forwarding four states support
- Forwarding STP frame to CPU port
- RSTP support
Support 16 ACL Entities Based On
- Ingress port or VLAN
- Destination/Source IP (specific or range)
- TCP/UDP Destination/Source port number (specific, > 1023, <=1023)
- Forwarding STP frame to CPU port
- Action : forward, to CPU, drop, priority, Q-in-Q tag
Configuration
- Pin initial setting
- 2-wire serial interface for configuration EEPROM
- 2-wire serial interface for low cost smart system application
Per Port 2 Counter (32 bit x 2) Selectable
- RX/TX packet count
- CRC error packet count
- Drop packet count
- Collision count
LED
- Direct mode
- 2-wire serial mode
Support Auto Test Function For Mass-production
- Auto generate test frames
- Shown the result on LED output
Interrupt Pin For PHY Mode/Link/SMI R/W
- Complete notification
Build-in SRAM Self Test (BIST)
Build-in Oscillator Circuit, Only One 25 MHz Crystal Needed
IO Voltage Selectable (3 groups)
90 nm Process, 208 Pin EDHS-QFP

新闻头条：
三星在显示屏领域又申请了一项专利，这个专利与之前申请的有所不同，因为这份专利申请是在世界知识产权组织（WIPO）出版号20180103132下提交的，涵盖的设备不仅是智能手机领域，它还适用于平板电脑、可穿戴设备，甚至是车显领域。

General Description :
The IP1725 is a cost effective and fully integrated single chip. It integrates a 25-port switch controller, an 3X octal PHY transceiver and SSRAM. Each of PHY transceiver complies with 802.3u specification and HP-license Auto MDI/MDIX.                              

It supports full smart switch functions, including IGMP snooping, 4 priority queues, TOS, TCP/UDP port number priority, 802.1Q VLAN, port security, protocol filter/forwarding and bandwidth control.

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