XC7K160T-2FF676I国宇航芯北京军工IC订货13632767652
商品详情
XC7K160T-2FF676I
FPGA Kintex-7 162240 Cells 28nm Technology 1V 676-Pin FCBGA
赛灵思公司（Xilinx, Inc.）是全球领先的可编程逻辑解决方案供应商，以先进解决方案推动全球不同市场的产品创新，广泛应用在各种应用领域的设计中。Xilinx 客户可以“快速”改变或升级产品特性及功能 – 例如，采用新标准或者针对具体应用重新配置硬件。这种“快速”的技术特点能够加快进入市场的速度、提供差异化的产品并降低成本。
服务的市场:
Xilinx 解决方案为各种终端市场推出最具有创新性的应用提供了坚实基础，这些市场包括：
航空航天及军用
汽车电子
广播
通信
消费品
工业、科研及医疗 (ISM)
Xilinx® 7 series FPGAs comprise three new FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:
Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
技术参数
Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.
High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to maximum rates of 6.6 Gb/s up to 28.05 Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.
Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.
Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.
Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, lidless flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.
Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.
