9,$7HFKQRORJLHV,QF
Processor Power Management Registers
Offset 13-10 - Processor Control ...................................... RW
........................................ always reads 0
31-5 Reserved
4
Throttling Enable (THT_EN).
3040 Silicon:
This bit determines the effect of
reading the "Processor Level 2" (P_LVL2) port:
0 No clock throttling. Reads from the Processor
Level 2 register are ignored.
1 Reading the "Processor Level 2" port enables
clock throttling by modulating the STPCLK#
signal with a duty cycle determined bits 3-1 of
this register.
3041 Silicon:
Setting this bit starts clock throttling
(modulating the STPCLK# signal) regardless
of the CPU state (i.e., it is not necessary to
read the "Processor Level 2" port to start clock
throttling).
The throttling duty cycle is
determined by bits 3-1 of this register.
3-1 Throttling Duty Cycle (THT_DTY)
This 3-bit field determines the duty cycle of the
STPCLK# signal when the system is in throttling
mode (the "Throttling Enable" bit is set to one and, in
3040 silicon, the "Processor Level 2" register is
read). The duty cycle indicates the percentage of
time the STPCLK# signal is asserted while the
Throttling Enable bit is set. The field is decoded as
follows:
000 Reserved
001 0-12.5%
010 12.5-25%
011 25-37.5%
100 37.5-50%
101 50-62.5%
110 62.5-75%
111 75-87.5%
........................................ always reads 0
0
Reserved
VT82C586B
Offset 14 - Processor Level 2 (P_LVL2) .......................... RO
........................................ always reads 0
7-0 Level 2
3040 Silicon:
Reads from this register put the
processor in the C2 clock state if the Throttling
Enable bit (Function 3 Rx10 bit-4) is set.
3041 Silicon:
Reads from this register put the
processor into the Stop Clock state (the VT82C586B
asserts STPCLK# to suspend the processor). Wake
up from Stop Clock state is by interrupt (INTR, SMI,
PWRBTN#, RTC wakeup, or pin toggle SCI).
Reads from this register return all zeros; writes to this register
have no effect.
Offset 15 - Processor Level 3 (P_LVL3) .......................... RO
........................................ always reads 0
7-0 Level 3
Reads from this register put the processor in the C3
clock state with the STPCLK# signal asserted.
3041
silicon:
wake up from Stop Clock state is by
interrupt (INTR, SMI, PWRBTN#, RTC wakeup, or
pin toggle SCI).
Reads from this register return all zeros; writes to this register
have no effect.
Revision 1.0
May 13, 1997
-48-
Register Descriptions
ETC [ ETC ]
