CAT24WC01/02/04/08/16
using either 24WC01 or 24WC02 device. All three
address pins are used for these densities. If only one
24WC02 is addressed on the bus, all three address pins
(A0, A1and A2) can be left floating or connected to V
SS
.
If only one 24WC01 is addressed on the bus, all three
address pins (A0, A1and A2) must be connected to V
SS
.
A total of four devices can be addressed on a single bus
when using 24WC04 device. Only A1 and A2 address
pins are used with this device. The A0 address pin is a
no connect pin and can be tied to V
SS
or left floating. If
only one 24WC04 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or con-
nected to V
SS
.
Only two devices can be cascaded when using 24WC08.
The only address pin used with this device is A2. The A0
and A1 address pins are no connect pins and can be tied
to V
SS
or left floating. If only one 24WC08 is being
addressed on the bus, the address pin (A2) can be left
floating or connected to V
SS
.
The 24WC16 is a stand alone device. In this case, all
address pins (A0, A1and A2) are no connect pins and
can be tied to V
SS
or left floating.
WP:
Write Protect
If the WP pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to V
SS
or left floating normal read/write opera-
tions are allowed to the device.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC01/
02, four CAT24WC04, two CAT24WC08, and one
CAT24WC16 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
the bus and responds with an acknowledge (on the SDA
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
5
This Material Copyrighted by Its Respective Manufacturer
Doc. No. 25051-00 3/98 S-1
ETC [ ETC ]
