CHRONTEL
t
HSW
HSYNC
t
HD
POut/
XCLK
Pixel
Data
AVR
SAV
CH7005C
t
P
P1
t
t
PH
t
SP1
t
PH 1
P0a
P0
P0b
P1
t
SP
t
t
HP1
HP
P1a
P2
P1b
P3
P2a
P4
P2b
P5
Figure 4: Non-multiplexed Data Transfers
When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data
streams), and the first byte of the ‘video timing reference code’ will be assumed to occur when a Cb sample would
occur – if the video stream was continuous. This is delineated in
Table 4
below.
Table 3. YCrCb Non-multiplexed Mode with Embedded Syncs
IDF#
Format
Pixel#
Bus Data
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
P0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P1
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
0
0
0
0
0
0
0
0
P2
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
1
YCrCb 16-bit
P3
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
P4
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P5
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P6
Y4[7]
Y4[6]
Y4[5]
Y4[4]
Y4[3]
Y4[2]
Y4[1]
Y4[0]
Cb4[7]
Cb4[6]
Cb4[5]
Cb4[4]
Cb4[3]
Cb4[2]
Cb4[1]
Cb4[0]
P7
Y5[7]
Y5[6]
Y5[5]
Y5[4]
Y5[3]
Y5[2]
Y5[1]
Y5[0]
Cr4[7]
Cr4[6]
Cr4[5]
Cr4[4]
Cr4[3]
Cr4[2]
Cr4[1]
Cr4[0]
In this mode, the S[7-0] byte contains the following data:
S[6]
S[5]
S[4]
=
=
=
F
V
H
=
=
=
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3-0] are ignored.
8
201-0000-025 Rev 2.1, 8/2/99
ETC [ ETC ]
