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UCC15701J 参数 Datasheet PDF下载

UCC15701J图片预览
型号: UCC15701J
PDF下载: 下载PDF文件 查看货源
内容描述: 电压型开关电源控制器\n [Voltage-Mode SMPS Controller ]
分类和应用: 开关控制器
文件页数/大小: 10 页 / 197 K
品牌: ETC [ ETC ]
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UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
Output Inhibit
During normal operation, OUT is driven high at the start
of a clock period and is driven low by voltages on CT, FB
or VSCLAMP.
The following conditions cause the output to be immedi-
ately driven low until a clock period starts where none of
the conditions are true:
1. I
LIM
> 0.2V
2. FB or SS is less than 0.8V
Current Limiting
ILIM is monitored by two internal comparators. The cur-
rent limit comparator threshold is 0.2V. If the current limit
comparator is triggered, OUT is immediately driven low
and held low for the remainder of the clock cycle, provid-
ing pulse-by-pulse over-current control for excessive
loads. This comparator also causes C
F
to be charged for
the remainder of the clock cycle.
If repetitive cycles are terminated by the current limit
comparator causing COUNT to rise above 4V, the shut-
down latch is set. The COUNT integration delay feature
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately
sets the shutdown latch. R
F
in parallel with C
F
resets the
COUNT integrator following transient faults. R
F
must be
greater than (4
R4)
(1 – D
MAX
).
Latched Shutdown
If ILIM rises above 0.6V, or COUNT rises to 4V, the shut-
down latch will be set. This will force OUT low, discharge
SS and COUNT, and reduce I
DD
to approximately 750 A.
When, and if, V
DD
falls below the UVLO stop threshold,
the shutdown latch will reset and I
DD
will fall to 130 A,
allowing the circuit to restart. If V
DD
remains above the
UVLO stop threshold (within the UVLO band), an alter-
nate restart will occur if VFF is momentarily reduced be-
low 1V. External shutdown commands from any source
may be added into either the COUNT or ILIM pins.
Voltage Feedforward
The voltage slope on CT is proportional to line voltage
over a 4:1 range and equals 2•VFF/(RT•CT). The capaci-
tor charging current is set by the voltage across R
T
.
V(RT) tracks VFF over a range of 0.8V to 3.2V. A chang-
ing line voltage will immediately change the slope of
V(CT), changing the pulse width in a proportional man-
ner without using the feedback loop, providing excellent
dynamic line regulation.
VFF is intended to operate accurately over a 4:1 range
between 0.8V and 3.2V. Voltages at VFF below 0.6V or
above 4.0V will initiate a soft stop cycle and a chip re-
start when the under/over voltage condition is removed.
Volt-Second Clamp
A constant volt-second clamp is formed by comparing
the timing capacitor ramp voltage to a fixed voltage de-
rived from the reference. Resistors R4 and R5 set the
volt-second limit. For a volt-second product defined as
VIN
t
ON(max)
, the required voltage at VSCLAMP is:
R
2
 •
V
IN
t
ON
(
max
)
R
1
+
R
2
.
R
T
C
T
The duty cycle limit is then:
(
)
V
VSCLAMP
, or
V
VFF
V
VSCLAMP
.
R
2
V
IN
• 
R
1
+
R
2
The maximum duty cycle is realized when the
feedforward voltage is set at the low end of the operating
range (V
FF
= 0.8V).
The absolute maximum duty cycle is:
D
MAX
=
V
VSCLAMP
V
REF
R
5
=
0 .8
0 .8
R
4
+
R
5
Frequency Set
The frequency is set by a resistor from RT to ground and
a capacitor from CT to ground. The frequency is approxi-
2
mately:
F
=
(
R
T
C
T
)
External synchronization is via the SYNC pin. The pin
has a 1.5V threshold , making it compatible with 5V and
3.3V CMOS logic. The input is level sensitive, with a high
input forcing the oscillator ramp low and the output low.
An active pull down on the SYNC pin allows it to be un-
connected when not used.
Gate Drive Output
The UCC35701/2 is capable of a 1A peak output current.
Bypass with at least 0.1 F directly to PGND. The capaci-
tor must have a low equivalent series resistance and in-
ductance. The connection from OUT to the power
MOSFET gate should have a 2 or greater damping re-
sistor and the distance between chip and MOSFET
should be minimized. A low impedance path must be es-
tablished between the MOSFET source (or ground side
of the current sense resistor), the V
DD
capacitor and
PGND. PGND should then be connected by a single path
(shown as RGND) to GND.
6
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