Low Power T1 PCM Repeaters/Transceivers — LXT312A/LXT315A
Figure 5. Digital Timing Characteristics
tF
tR
RCLK
tTH
tTSU
TTIP,
TRIN
(with external pull-up)
tPW
Table 6. Digital Timing Characteristics (Over Recommended Range)
Parameter
Symbol
Min
Typ1
Max
Unit
Driver pulse width
t
PW
299
–
324
–
349
15
18
–
ns
ns
ns
ns
ns
Driver pulse imbalance
–
Rise and fall time (any digital output2)
Setup time - TTIP/TRING to RCLK
Hold time - TTIP/TRING from RCLK
t
R / t
F
–
–
t
TSU
90
90
–
t
TH
–
–
1. Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to production testing.
2. Measured with CLOAD ≤ 10 pF, RLOAD > 100 kΩ.
4.1
Test Setups
4.1.1
Introduction
Both the LXT312A and LXT315A are fully tested (100% AC and DC parameters) using inputs
generated by Intel’s proprietary transmission line and network simulator. Device testing includes
receiver jitter tolerance, jitter transfer and interference margin, and receiver immunity to Gaussian
and 60 Hz noise. Specifications and bench test setups are shown in Figure 6 through Figure 13.
4.1.2
4.1.3
Receiver Jitter Tolerance Testing
Receiver jitter tolerance meets the template shown in Figure 6, when operated at line losses from 0
to 36 dB. Figure 8 shows the setup used for jitter tolerance testing.
Receiver Jitter Transfer Testing
Receiver jitter transfer meets the template shown in Figure 7, when operated with line losses from
0 to 36 dB and input jitter amplitude of 0.15 UI peak-to-peak. Jitter gain at a given frequency is
defined as the difference between intrinsic jitter and additive jitter at the measurement frequency,
divided by the amplitude of the input jitter. Figure 9 shows the setup used for jitter transfer testing.
Datasheet
13
ETC [ ETC ]
